CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 68

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25. Voltage Vs CPU Frequency Characteristics
Running the CPU at 24 MHz requires a minimum voltage of
4.75 V. This applies to any CPU speed above 12 MHz, so using
an external clock between 12–24 MHz must also adhere to this
requirement. Operating the CPU at 24MHz when the supply
voltage is below 4.75 V can cause undesired behavior and must
be avoided.
Many enCoRe II applications use USB Vbus 5 V as the power
source for the device. According to the USB specification,
voltage can be less than 4.75 V on Vbus (if the USB port is a low
power port the voltage can be between 4.4 V and 5.25 V). Even
for externally powered 5 V applications, developers must
consider that on power up and power down voltage is less than
4.75V for some time. Firmware must be implemented properly to
prevent undesired behavior.
Use of 24 MHz requires the use of the high POR trip point of
approximately 4.55–4.65 V (Register LVDCR 0x1E3,
PORLEV[1:0] = 10b). This setting is sufficient to protect the
device from problems due to operating at low voltage with CPU
speeds above 12 MHz. This must be set before setting the CPU
speed to greater than 12 MHz. For devices with slow power
ramps, changing the POR threshold to the high level may result
in one or more resets of the device as power ramps through the
chip default POR set point of approximately 2.6 V up through the
high POR set point.
If multiple resets are undesirable for slow power ramps, then
firmware must do the following:
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Document 38-08035 Rev. *N
Note
6. In Master mode, first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
Set the Low Voltage Detection circuit (Register LVDCR 0x1E3,
VM[2:0]) for one of the set points above the POR (VM[2:0] =
110 b ~4.73 V or 111b ~4.82 V).
Monitor the LVD until voltage is above the trip point (Register
VLTCMP 0x1E4, bit 1 is clear).
5.50
4.75
4.00
Figure 25-1. Voltage vs CPU Frequency Characteristics
93 KHz
CPU Frequency
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If the supply voltage dips below 4.75 V and the application can
tolerate running at a CPU speed of 12 MHz, then application
firmware may also implement the following to minimize the
chance of a reset event due to a voltage transient:
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Debounce the indication to ensure that voltage is above the set
point for possible noisy supplies.
Set the POR to the high set point.
Shift CPU speed to 24 MHz.
Set the LVD for one of the desired high setting (~4.73 V or
~4.82 V).
Enable the LVD interrupt.
In the LVD ISR, reduce CPU speed to 12 MHz and shift the
POR to a lower threshold.
Firmware can monitor for VLTCMP to clear within the normal
application main loop.
Debounce the indication to ensure voltage is above the set
point.
Shift the POR to the high set point.
Shift the CPU to 24 MHz.
12 MHz
24 MHz
CY7C63310, CY7C638xx
Page 68 of 86
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