CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 48

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 16-2. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W]
Table 16-3. Capture Interrupt Status (TCAPINTS) [0x2C] [R/W]
Document 38-08035 Rev. *N
Bit [7:4]: Reserved
Bit 3: Cap1 Fall Enable
0 = Disable the capture 1 falling edge interrupt
1 = Enable the capture 1 falling edge interrupt
Bit 2: Cap1 Rise Enable
0 = Disable the capture 1 rising edge interrupt
1 = Enable the capture 1 rising edge interrupt
Bit 1: Cap0 Fall Enable
0 = Disable the capture 0 falling edge interrupt
1 = Enable the capture 0 falling edge interrupt
Bit 0: Cap0 Rise Enable
0 = Disable the capture 0 rising edge interrupt
1 = Enable the capture 0 rising edge interrupt
Bit [7:4]: Reserved
Bit 3: TIO1 Fall Active
0 = No event
1 = A falling edge has occurred on TIO1
Bit 2: TIO1 Rise Active
0 = No event
1 = A rising edge has occurred on TIO1
Bit 1: TIO0 Fall Active
0 = No event
1 = A falling edge has occurred on TIO0
Bit 0: TIO0 Rise Active
0 = No event
1 = A rising edge has occurred on TIO0
Note The interrupt status bits must be cleared by firmware to enable subsequent interrupts. This is achieved by writing a ‘1’ to
the corresponding Interrupt status bit.
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
7
–
0
7
–
0
6
–
0
6
–
0
Reserved
Reserved
5
–
0
5
–
0
4
–
0
4
–
0
Cap1 Fall
TIO1 Fall
Enable
Active
R/W
R/W
3
0
3
0
TIO1 Rise Active
Cap1 Rise
Enable
R/W
R/W
CY7C63310, CY7C638xx
2
0
2
0
Cap0 Fall
TIO0 Fall
Enable
Active
R/W
R/W
1
0
1
0
TIO0 Rise Active
Cap0 Rise
Enable
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R/W
R/W
0
0
0
0
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