STLC5048TR STMicroelectronics, STLC5048TR Datasheet - Page 29

• Manufacturer Part Number: STLC5048TR
• Description: IC CODEC/FILTER PROGR 4CH 64TQFP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of STLC5048TR

• Data Interface: PCM Audio Interface
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5048
5.10
For static I/O configuration, MCn bits are the interrupt mask bits related to CSn that are
configured as I/O lines.
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MC3 and MC1 bit are not used in static mode.
Input lines with persistency check generate interrupt if the changed status remains stable
longer than the time programmed in the persistency check register PCHKA/B. Line without
persistency check generate an immediate interrupt request.
Mask register has no effect on those pins configured as outputs, those pins will not generate
interrupt
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Alarm register (ALARM)
Addr=14h; reset value=01h
Read-only
Table 29.
POR=0: No power on reset is detected during operation.
POR=1: A power on reset is detected during operation.
The ALARM register is cleared after reading operation only if signals (alarm cause) are
inactive.
Bit7
MC0=1: The corresponding I/O cannot generate interrupt independently of DMASK
setting.
MC0=0: The corresponding I/O can generate interrupt if a change of status is detected
depending of DMASK setting.
MC2=1: The corresponding I/O cannot generate interrupt independently of DATA3_L
setting (bit 3..0).
MC2=0: The corresponding I/O can generate interrupt if a change of status is detected
depending of DATA3_L setting (bit 3..0).
MCF=1: The corresponding alarm bit (CKF) doesn’t generate interrupt.
MCF=0: The corresponding alarm bit (CKF) can generate interrupt.
MTV=1: The corresponding alarm bit (TV) doesn’t generate interrupt.
MTV=0: The corresponding alarm bit (TV) can generate interrupt.
MPCM =1: The IPCM interrupt is masked (generation disabled).
MPCM =0: The IPCM interrupt is enabled (generation enabled).
1
0
Alarm register (ALARM) bits
Bit6
0
0
Bit5
0
0
Bit4
1
0
Bit3
0
0
Bit2
1
0
Register description
Bit1
0
0
POR
Bit0
0
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