STLC5048TR STMicroelectronics, STLC5048TR Datasheet - Page 20

• Manufacturer Part Number: STLC5048TR
• Description: IC CODEC/FILTER PROGR 4CH 64TQFP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of STLC5048TR

• Data Interface: PCM Audio Interface
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.3 V ~ 5 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional description
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SLIC control interface
The device provides 12 I/O pins and 4 CS signals. The interface can work in dynamic or
static mode. This can be selected by means of STA bit of the CONF register:
●
●
DC SLIC programmability
Three additional pins are used to select the on-hook/off-hook detection threshold and the
line card limitation of the STLC3080 SLIC. This two values are programmed by ILIM and ITH
registers. The programming of these two registers must be done before the filter coefficients
download.
The VBG input pin must be connected to the IREF pin of the STLC3080.
When the L3235N is used in kit with STLC5048 the ILIM, ITH and VBG pin must be not
connected.
Built-in test
By means of TONEG register it is possible to inject a tone of variable frequency (25 Hz, 1
and 3 kHz) and 0 dBm0 amplitude into the receive path, replacing any signal coming from
the PCM interface. This test can be performed on every channel.
Setting the proper bit of the PCMCOM register is also possible to read/write the PCM data
coming from the transmit path via the MCU interface (PCMRD/PCMWD registers). This
feature can be enabled only on one channel per time.
These two features can be used to test the line interface operation.
Table 7.
Dynamic mode: the I/O pins are configured as input or output by means of DIR register.
The CS signals are used to select the different SLIC interface. In this case the I/O pin
can be multiplexed. The data loaded from SLIC #n via I/O pins configured as input can
be read in the DATAn register. The data written in a DATAn register will be loaded on the
I/O pins configured as output when the CSn signal will be active.
Static mode: The CS signal can be used as I/O pins. They can be configured as input
or output I/O by means of DATA1 register. The data corresponding to the CS signal can
be read or written by means of DATA2 register. All data related to the other I/O pins can
be read or written by means of DATA0 register.
Addr
00h
01h
02h
03h
04h
05h
06h
07h
Register addresses
DATA0-H
DATA1-H
DATA2-H
DATA0-L
DATA1-L
DATA2-L
DIR-H
Name
DIR-L
I/O direction (bit 7-0)
I/O direction (bit 11-8)
I/O data ch#0 (bit 7-0)
I/O data ch #0 (bit 11-8)
I/O data ch#1 (bit 7-0)
I/O data ch #1 (bit 11-8)
I/O data ch#2 (bit 7-0)
I/O data ch #2 (bit 11-8)
Description
STLC5048