MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 97

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Bus Operation
asserted in any asynchronous system. If this maximum delay time is violated, the QUICC
may exhibit erratic behavior.
4.2.5 Synchronous Operation with DSACKx
Although cycles terminated with DSACKx are classified as asynchronous, cycles terminated
with DSACKx can also operate synchronously in that signals are interpreted relative to clock
edges. The devices that use these cycles must synchronize the response to the QUICC
clock (CLKO1) to be synchronous. Since the devices terminate bus cycles with DSACKx,
the dynamic bus sizing capabilities of the QUICC are available. The minimum cycle time for
these cycles is also three clocks. To support systems that use the system clock to generate
DSACKx and other asynchronous inputs, the asynchronous input setup time and the asyn-
chronous input hold time are given. If the setup and hold times are met for the assertion or
negation of a signal, such as DSACKx, the QUICC is guaranteed to recognize that signal
level on that specific falling edge of the system clock. If the assertion of DSACKx is recog-
nized on a particular falling edge of the clock, valid data is latched into the QUICC (for a read
cycle) on the next falling clock edge if the data meets the data setup time. In this case, the
parameter for asynchronous operation can be ignored. The timing parameters are described
in Section 10 Electrical Characteristics.
If a system asserts DSACKx for the required window around the falling edge of S2 and
obeys the proper bus protocol by maintaining DSACKx (and/or BERR/HALT) until and
throughout the clock edge that negates AS (with the appropriate asynchronous input hold
time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles
terminated with DSACKx (three clocks per cycle). When BERR (or BERR and HALT) is
asserted after DSACKx, BERR (and HALT) must meet the appropriate setup time prior to
the falling clock edge one clock cycle after DSACKx is recognized. This setup time is critical,
and the QUICC may exhibit erratic behavior if it is violated. When operating synchronously,
the data-in setup and hold times for synchronous cycles may be used instead of the timing
requirements for data relative to DS.
4.2.6 Fast Termination Cycles
With an external device that has a fast access time, the memory controller circuits can pro-
vide a two-clock external bus transfer. Since the memory controller circuits are driven from
the system clock, the bus cycle termination is inherently synchronized with the system clock.
Refer to Section 6 System Integration Module (SIM60) for more information on chip selects
and the DRAM controller. To use the fast termination (cycle length is two clocks) option, an
external device should be fast enough to have data ready, within the specified setup time,
by the falling edge of S4. Figure 4-14 shows the DSACKx timing for a read with two wait
states, followed by a fast termination read and write.
MOTOROLA
MC68360 USER’S MANUAL
4-21
For More Information On This Product,
Go to: www.freescale.com