MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 810

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Applications
MC68EC030 signals must be synchronized internally with the QUICC, additional wait states
will be introduced. For applications with any significant level of external memory accesses,
this would limit the additional cost/performance benefit of a 40-MHz MC68EC030. The sec-
ond reason for needing an external DRAM controller is found by taking a closer look at how
the QUICC memory controller would interface with a high-speed MC68EC030.
The signal interaction that would occur if two consecutive writes were performed is shown
in Figure 9-27. After the assertion of DSACKx by the QUICC on a 25-MHz edge, the 40-MHz
MC68EC030 would recognize DSACKx on the next falling 40-MHz edge, and proceed to
negate AS one cycle after that. The problem is that the MC68EC030 begins another write
cycle one-half MC68EC030 clock cycle later, and one-half clock cycle into that write cycle,
AS is asserted. In asynchronous mode, since external signals are synchronized to the
QUICC on QUICC falling clock edges, at 25 MHz there is no guarantee that the QUICC will
see the negated AS, which is present for only one MC68EC030 cycle (25 ns).
To take advantage of the QUICC memory controller capabilities, it would be necessary for
designers to address issues like this. This task would need to be done with external hard-
ware, such as a state machine, to ensure conformity to the QUICC electrical specifications.
A second option would be to use an external memory controller and use the QUICC to gen-
erate only the chip selects. Either option will require additional hardware.
Designers considering an asynchronous interface also need to address timing issues asso-
ciated with using the QUICC memory controller capabilities. When the QUICC provides the
bus control for a system, it is offered at the speed of the QUICC. Therefore, a 40-MHz
MC68EC030 will access the bus at 25 MHz. In addition, since the MC68EC030 signals must
be synchronized with the QUICC, additional wait states will be introduced. Since the exact
timing will depend on the type and speed of memory access, no exhaustive analysis is pro-
vided. The primary advantage of an MC68EC030 over the CPU32+ would be the onboard
cache and the new instructions. Whether this advantage would outweigh the potential timing
disadvantages will vary depending on system hardware and software considerations.
In any case, the QUICC makes a valuable peripheral chip in an MC68030-based design
because of the wealth of serial functions it offers, even if the memory controller on the
QUICC is not extensively used in such a design.
9.9 PUTTING A BACKGROUND DEBUG MODE CONNECTOR ON A
TARGET BOARD
The QUICC, as well as other members of the M68300 family of integrated processors, con-
tains a background debug mode (BDM). The BDM is essentially a debugger that is built into
the CPU32+ on the QUICC. The user can communicate with the CPU32+ through the BDM
port on the QUICC.
The BDM pins on the QUICC can be used in a number of ways. First, emulator manufactur-
ers use these pins in the development of their QUICC emulator products. This use of the
BDM pins is usually unseen and completely transparent to the user. Second, vendors of
debug monitors use the BDM pins for offering low-cost debug monitor products. In this way,
the target board can be monitored and debugged using a debugger resident on a PC. Third,
some users develop their own BDM interface software to solve special debugging and test-
9-90
MC68360 USER’S MANUAL
MOTOROLA
For More Information On This Product,
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