MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 482

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
FRZ—Freeze Transmission
RZS—Receive Zero Stop Bits
SYN—Synchronous Mode
DRT—Disable Receiver While Transmitting
7-158
This bit allows the user to halt the UART transmitter and continue transmission from the
same point at a later time.
The RZS bit configures the UART receiver to receive data without stop bits. This config-
uration is useful in V.14 applications where UART data is supplied synchronously and all
stop bits of a particular character may be omitted for the purpose of across-network rate
adaptation. RZS should only be set if the SYN bit is also set.
0 = Normal operation. If the UART was previously frozen, the UART resumes trans-
1 = The UART completes transmission of any data already transferred to the UART
0 = The receiver operates normally with at least one stop bit required between charac-
1 = The receiver will continue reception if a missing stop bit is detected. If the stop bit
0 = Normal asynchronous operation. Note that the user would normally program the
1 = Synchronous UART using 1 clock. Note that the user would normally program the
0 = Normal operation
1 = While data is being transmitted by the SCC, the receiver is disabled, being gated
mission from the next character in the same buffer that was frozen.
FIFO (the number of characters depends on the TFL bit in the GSMR) and then
freezes (stops transmitting data). After this bit is reset, transmission will proceed
from the next character.
ters. A framing error is issued upon a missing stop bit, and a break status is set if
a character with all-zero data bits is received with a zero stop bit.
is a zero, then the next bit is considered as the first data bit of the next character.
A framing error is issued if a stop bit is missing, but a break status will be reported
only after back-to-back reception of two break characters without stop bits.
TENC and RENC bits in the GSMR to NRZ, and must select either 8 , 16 , or 32
in the RDCR and TDCR bits of the GSMR (16 is the recommended value for most
applications).
TENC and RENC bits in the GSMR to NRZ, and must select the RDCR and TDCR
bits in the GSMR to be 1 mode.
A one bit is transferred with each clock and is synchronous to the clock. (As with
the other modes, the clock may be provided internally or externally.) This mode is
sometimes referred to as isochronous operation of a UART channel.
by the internal RTS signal. This configuration is useful if the UART is configured
onto a multidrop line and the user does not wish to receive his own transmission.
RAM values, and automatically accepts or discards the data that follows the ad-
dress.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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