MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 741

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Applications
9.3.4.2 SYSTEM RAM. The QUICC contains 2560 bytes of dual-port RAM rather than 576
bytes. Both the MC68302 and the QUICC split the dual-port RAM into two parts: user data
RAM and parameter RAM.
The user data RAM of the QUICC may be used in the same way it is used in the MC68302.
However, on the QUICC, it has one major additional feature—it may be used to store buffer
descriptors for serial data. (In fact, the QUICC has no special location for buffer descriptors
in the dual-port RAM. They may be mapped anywhere.) Thus, the user should plan on the
user data RAM being used for buffer descriptors, in addition to whatever the RAM was being
used for in the MC68302 application.
The parameter RAM of the MC68302 is very similar to the parameter RAM on the QUICC,
except that there is no special location for buffer descriptors on the QUICC. This gives the
user the ability to choose the location and number of buffer descriptors for each serial chan-
nel.
The specific protocol parameter area of the MC68302 is available on the QUICC. On the
QUICC there are four such areas; whereas, on the MC68302 there are only three. Like the
MC68302, each specific protocol parameter area is comprised of two parts—a protocol
independent part that is common to all SCCs, regardless of their protocol, and a protocol
specific part that is unique to each SCC, based on the protocol.
On the MC68302, the SMCs and SCP were given special locations for buffer descriptors and
parameter areas. On the QUICC, the SMCs and SPI are controlled like the SCCs, with buffer
descriptors that may be located anywhere in the user RAM, and with a specific protocol
parameter RAM. In fact, all the QUICC SCCs, SMCs, and SPI have a common subset of
parameter RAM.
The following description will discuss the buffer descriptors, protocol-independent parame-
ter RAM, and protocol-dependent parameter RAM for the MC68302 and the QUICC.
9.3.4.2.1 Buffer Descriptors. The buffer descriptors for the MC68302 and the QUICC are
essentially the same.
The status and control field is a 16-bit field on both the MC68302 and the QUICC. All bits
are in their original positions with the following exceptions: the X-bit is removed, since the
determination of an internal or external address is made by the full address decoding on the
QUICC. The user may still set this bit location without harm. In UART mode, the PM and A
bits had to be moved. In BISYNC mode, the B-bit had to be moved. Additional status and
control bits were added on the QUICC in previously unused bit positions.
The data length field is identical between the MC68302 and the QUICC.
The data buffer pointer is the same between parts; however, on the QUICC, all 32 bits are
used. Additionally, if the receive FIFO is set to 32-bit-wide mode, then the data buffer pointer
must be aligned to a long word.
9.3.4.2.2 Protocol-Independent Parameter RAM Values. These values are very similar
on both devices.
MOTOROLA
MC68360 USER’S MANUAL
9-21
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