MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 538

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
The status and control bits are prepared by the user before transmission and are set by the
CP after the buffer has been transmitted.
R—Ready
W—Wrap (Final BD in Table)
I—Interrupt
L—Last in Message
TB—Transmit BCS
CM—Continuous Mode
7-214
This bit is valid only when the L-bit is set.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
0 = The data buffer associated with this BD is not ready for transmission. The user is
1 = The data buffer, which has been prepared for transmission by the user, has not
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been serviced.
1 = Either TX or TXE in the BISYNC event register will be set when this buffer has been
0 = The last character in the buffer is not the last character in the current block.
1 = The last character in the buffer is the last character in the current block. The trans-
0 = Transmit the SYN1–SYN2 sequence or idle (according to the RTSM bit in the
1 = Transmit the BCS sequence after the last character. The BISYNC controller will
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
free to manipulate this BD or its associated data buffer. The CP clears this bit after
the buffer has been transmitted or after an error condition is encountered.
been transmitted or is currently being transmitted. No fields of this BD may be writ-
ten by the user once this bit is set.
receive incoming data into the first BD in the table (the BD pointed to by TBASE).
The number of Tx BDs in this table is programmable, and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
serviced by the CP, which can cause an interrupt.
mitter will enter (remain in) normal mode after sending the last character in the buff-
er and the BCS (if enabled).
GSMR) after the last character in the buffer.
also reset the BCS generator after transmitting the BCS.
data buffer to be retransmitted automatically when the CP next accesses this BD.
15
R
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
11
L
MC68360 USER’S MANUAL
Go to: www.freescale.com
TB
10
CM
TX DATA BUFFER POINTER
9
DATA LENGTH
BR
8
TD
7
TR
6
B
5
—
4
—
3
—
2
MOTOROLA
UN
1
CT
0