MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 809

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Applications
9.8.4 Interfacing Multiple QUICCs to an MC68EC030
It is possible to interface multiple QUICCs to an MC68EC030. The first QUICC can be con-
figured as previously shown in this subsection. Additional QUICCs should be configured as
noted in the following list:
9.8.5 Using a Higher Speed MC68EC030 Master with the QUICC
It is possible to interface an MC68EC030 and QUICC through an asynchronous bus. This
should allow an external master to operate at higher frequencies than those of the QUICC
with minimal effort. As of this writing, the QUICC top frequency is 25 MHz; whereas,
MC68EC030s are available up to 40 MHz. One potentially attractive option for a designer
would be to consider disabling the CPU32+ core and increasing system performance by
adding a 40-MHz MC68EC030 asynchronously. While this option is available, it is important
for the designer to consider what effects a higher speed MC68EC030 would ultimately have
on system cost and performance over using the QUICC CPU32+ at a lower frequency.
For the designer to take full advantage of a high-speed MC68EC030, it will be necessary to
add additional glue to that shown in Figure 9-27. The additional circuitry takes the form of a
DRAM controller, which is used instead of using the QUICC memory controller. The need
for the additional logic is twofold. First, if the QUICC memory controller capabilities are used,
all memory accesses would be at the clock rate of 25 MHz. In addition, since the
9-89
The AM27–AM11 bits should be programmed to determine the block size of the chip se-
lect or RASx line. This should be the total number of bytes in each memory array except
for the EEPROM, which should be 32 Kbytes, rather than 8 Kbytes.
FCM3–FCM0 may be set to all ones to allow the chip select or RASx line to assert on all
function codes except CPU space (interrupt acknowledge). It is advisable to program
FCM3–FCM0 to ones, at least during the initial stages of debugging.
BCYC1–BCYC0 is not applicable.
PGME should be set to enable page mode and cleared otherwise.
SPS1–SPS0 should be cleared (32-bit SRAM port).
DSSEL should be set only if this is a DRAM bank.
• The additional QUICCs should have their CONFIG2–CONFIG0 pins configured for
• The MBAR of the additional QUICCs should be programmed using the MBARE pin and
• An external bus arbiter is required to take the bus request of the additional QUICC
• An external interrupt prioritizer is required to determine which QUICC IOUT2–IOUT0
slave mode, global chip select disabled , and MBAR at $003FF04.
MBARE register as described in the Section 6 System Integration Module (SIM60).
(which is an output because of the CONFIG2–CONFIG0 pins) and prioritize it with the
other QUICCs, present it to the MC68EC030, and issue a bus grant to the appropriate
QUICC.
pins are currently routed to the MC68EC030. Alternatively, the additional QUICC
should have its interrupts brought out on a single RQOUT pin, which is routed to one of
the original QUICC interrupt inputs. This would eliminate the external logic.
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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