MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 79

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

4.1.1 Bus Control Signals
The QUICC initiates a bus cycle by driving the address, size, function code, and read/write
outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with the FC signals. SIZ1
and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle
(consisting of one or more bus cycles). Table 4-3 lists the encoding of SIZ1 and SIZ0. These
signals are valid while AS is asserted.
The R/W signal determines the direction of the transfer during a bus cycle. Driven at the
beginning of a bus cycle, R/W is valid while AS is asserted. R/W only transitions when a write
cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive
write cycles.
The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write
operation and remains asserted until completion of the final bus cycle of the operation.
4.1.2 Function Codes (FC3–FC0)
The FCx signals are outputs that indicate one of 16 address spaces to which the address
applies. Fifteen of these spaces are designated as either a normal or DMA cycle, user or
supervisor, and program or data spaces. One other address space is designated as CPU
space to allow the CPU32+ to acquire specific control information not normally associated
with read or write bus cycles. The FCx signals are valid while AS is asserted.
Function codes (see Table 4-1) can be considered as extensions of the 32-bit address that
can provide up to eight different 4-Gbyte address spaces. Function codes are automatically
generated by the CPU32+ to select address spaces for data and program at both user and
supervisor privilege levels, and a CPU address space for processor functions. User pro-
grams access only their own program and data areas to increase protection of system integ-
rity and can be restricted from accessing other information. The S-bit in the CPU32+ status
register is set for supervisor accesses and cleared for user accesses to provide differentia-
tion. Refer to 4.4 CPU Space Cycles for more information.
MOTOROLA
3
0
0
0
0
0
0
0
0
1
Freescale Semiconductor, Inc.
Function Code Bits
For More Information On This Product,
Table 4-1. Address Space Encoding
2
0
0
0
0
1
1
1
1
x
MC68360 USER’S MANUAL
Go to: www.freescale.com
1
0
0
1
1
0
0
1
1
x
0
0
1
0
1
0
1
0
1
x
Reserved (Motorola)
User Data Space
User Program Space
Reserved (User)
Reserved (Motorola)
Supervisor Data Space
Supervisor Program Space
Supervisor CPU Space
DMA space
Address Spaces
Bus Operation
4-3