MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 278

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Integration Module (SIM60)
6.9.3.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to exter-
nal interrupt levels that require an autovector response. Setting a bit allows the SIM60 to
assert an internal AVEC during the interrupt acknowledge cycle in response to the specified
interrupt request level. This register can be read and written at any time.
6.9.3.3 RESET STATUS REGISTER (RSR). The RSR contains a bit for each reset source
to the SIM60. A set bit indicates the last type of reset that occurred. The RSR is updated by
the reset control logic when the reset is complete. After power-up reset, the POW bit and
the EXT bit are set. Other bits may be set after different kinds of reset occur. Since this reg-
ister is only cleared upon a power-up reset, the user should clear this register after every
reset so that the cause of the most recent reset may be easily determined.
A bit is cleared by writing a one (writing a zero does not affect a bit’s value). More than one
bit may be cleared at a time. The register may be read at any time. For more information,
see Section 4 Bus Operation.
EXT—External Total System Reset (Hard Reset)
POW—Power-Up Reset
6-34
1 = The last reset was caused by an external signal driving RESETH. This will reset all
1 = The last reset was caused by the power-up reset circuit.
the QUICC's peripherals to the state they had at power-up reset. This reset, which
is also referred to as system reset or hardware reset, has the same effect in the
system as a power-up reset.
If, a SIM60 interrupt source shares a level with the CPM, write
either $F or $1 to this register. Since the CPM interrupt arbitra-
tion ID is always 8, the $F gives the SIM60 source higher priority
than the CPM source(s), and a $1 gives the interrupt source low-
er priority than the CPM source(s). This field should never be
programed to 0.
The IARB field in the MCR must contain a value other than $0
for the SIM60 to produce an autovector for external interrupts.
RESET:
EXT
AV7
Freescale Semiconductor, Inc.
7
7
0
For More Information On This Product,
POW
AV6
6
6
0
MC68360 USER’S MANUAL
Go to: www.freescale.com
SW
AV5
5
5
0
DBF
AV4
4
NOTE
NOTE
4
0
AV3
—
3
3
0
LOC
AV2
2
2
0
SUPERVISOR ONLY
SUPERVISOR ONLY
SRST
AV1
1
1
0
SRSTP
0
0
0
-
MOTOROLA