MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 580

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
Heartbeat . Some transceivers have a self-test feature called “heartbeat” or “signal quality
error.” To signify a good self-test, the transceiver indicates a collision to the QUICC within
20 clocks after completion of a frame transmitted by the Ethernet controller. This indication
of a collision does not imply a real collision error on the network, but is rather an indication
that the transceiver still seems to be functioning properly. This is called the heartbeat con-
dition.
If the HBC bit is set in the Ethernet mode register and the heartbeat condition is not detected
by the QUICC after a frame transmission, then a heartbeat error occurs. When this error
occurs, the channel closes the buffer, sets the HB bit in the Tx BD, and generates the TXE
interrupt if it is enabled.
7.10.23.16.2 Reception Errors. The following paragraphs describe various types of Ether-
net reception errors.
Overrun Error . The Ethernet controller maintains an internal FIFO for receiving data. If a
receiver FIFO overrun occurs, the channel writes the received data byte to the internal FIFO
over the previously received byte. The previous data byte and the frame status are lost. The
channel closes the buffer, sets the OV bit in the Rx BD, sets RXF in the Ethernet event reg-
ister, and increments the discarded frame counter (DISFC). The receiver then enters the
hunt mode.
Busy Error. A frame was received and discarded due to lack of buffers. The channel sets
BSY in the Ethernet event register and increments the discarded frame counter (DISFC).
Nonoctet Error (Dribbling Bits) . The Ethernet controller can handle up to seven dribbling bits
when the receive frame terminates nonoctet aligned. The Ethernet controller checks the
CRC of the frame on the last octet boundary. If there is a CRC error, then the frame nonoctet
aligned (NO) error is reported, the RXF bit is set, and the alignment error counter (ALEC) is
incremented. If there is no CRC error, then no error is reported.
CRC Error . When a CRC error occurs, the channel closes the buffer, sets the CR bit in the
Rx BD, and sets the RXF bit. The channel also increments the CRC error counter (CRCEC).
After receiving a frame with a CRC error, the receiver enters hunt mode. CRC checking can-
not be disabled, but the CRC error may be ignored if checking is not required.
7.10.23.17 ETHERNET MODE REGISTER (PSMR). The Ethernet mode register is a 16-
bit, memory-mapped, read-write register that controls the SCC operation. The term Ethernet
mode register refers to the PSMR of the SCC when that SCC is configured for Ethernet. This
register is cleared at reset.
7-256
HBC
15
FC
14
RSH
13
The definition of what constitutes a late collision is made in the
LCW bit in the PSMR.
IAM
12
11
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CRC
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10
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PRO
9
BRO
NOTE
8
SBT
7
LPB
6
SIP
5
LCW
4
3
NIB
2
MOTOROLA
1
FDE
0