MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 337

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

TM_BASE. The actual RISC timers are located by the user as a small block of memory in
the dual-port RAM. TM_BASE is the offset from the beginning of dual-port RAM where that
block resides. The user should allocate 4 bytes at TM_BASE for each timer used (64 bytes
at TM_BASE if all 16 timers are used). If less than 16 timers are used, the timers should
always be allocated in ascending order (RISC timer 0, RISC timer 1, etc.) to save space. For
example, if the user only needs two timers, then 8 bytes are required at location TM_BASE
as long as the user only enables RISC timer 0 and RISC timer 1.
TM_ptr. This value is used exclusively by the RISC to point to the next timer to be accessed
in the timer table. It should not be modified by the user.
R_TMR. This value is used exclusively by the RISC to store the mode of the timer: one-shot
(bit is zero) or restart (bit is one). R_TMR should not be modified by the user. The SET
TIMER command should be used instead.
R_TMV. This value is used exclusively by the RISC to store whether a timer is currently
enabled. A bit is a one if the corresponding timer is enabled. R_TMV should not be modified
by the user. The SET TIMER command should be used instead.
TM_cmd. This value is used as a parameter location when the SET TIMER command is
issued. The user should write this location prior to issuing the SET TIMER command. This
parameter is defined as follows:
V—Valid
R—Restart
MOTOROLA
31
This bit should be set to enable the timer and cleared to disable the timer.
This bit should be set for an automatic restart or cleared for a one-shot operation of the
timer.
V
30
R
TM_BASE should always be aligned to a long-word boundary
(i.e., evenly divisible by 4).
29
Timer Base + 00
Timer Base + 02
Timer Base + 04
Timer Base + 06
Timer Base + 08
Timer Base + 0C
NOTE: Boldfaced items are initialized by the user.
Address
Table 7-2. RISC Timer Table Parameter RAM
Freescale Semiconductor, Inc.
For More Information On This Product,
—
TM_BASE
TM_cmd
R_TMR
R_TMV
TM_cnt
TM_ptr
Name
MC68360 USER’S MANUAL
Go to: www.freescale.com
20
NOTE
Width
Word
Word
Word
Word
Long
Long
TIMER NUMBER
19
RISC Timer Table Base Address
RISC Timer Table Pointer
RISC Timer Mode Register
RISC Timer Valid Register
RISC Timer Command Register
RISC Timer Internal Count
16
Description
15
TIMER PERIOD (16 BITS)
RISC Timer Tables
7-13
0