MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 120

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Bus Operation
In the second case, in which BERR is asserted after DSACKx is asserted, BERR must be
asserted within the time specified for purely asynchronous operation, or it must be asserted
and remain stable during the sample window around the next falling edge of the clock after
DSACKx is recognized. If BERR is not stable at this time, the QUICC may exhibit erratic
behavior. BERR has priority over DSACKx. In this case, data may be present on the bus but
may not be valid. This sequence can be used by systems that have memory error detection
and correction logic and by external cache memories.
4.5.2 Retry Operation
When both BERR and HALT are asserted by an external device during a bus cycle, the
QUICC enters the retry sequence shown in Figure 4-31. A delayed retry, which is similar to
the delayed bus error signal described previously, can also occur (see Figure 4-32). The
QUICC terminates the bus cycle, places the control signals in their inactive state, and does
not begin another bus cycle until the BERR and HALT signals are negated by external logic.
After a synchronization delay, the QUICC retries the previous cycle using the same access
information (address, function code, size, etc.). BERR should be negated before S2 of the
retried cycle to ensure correct operation of the retried cycle.
4-44
FC3–FC0
DSACKx
A31–A0
D31–D0
CLKO1
BERR
R/W
DS
AS
Figure 4-30. Late Bus Error with DSACKx
S0
Freescale Semiconductor, Inc.
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S2
CYCLE
WRITE
MC68360 USER’S MANUAL
Go to: www.freescale.com
S4
PROCESSING
INTERNAL
S0
S2
STACK
WRITE
S4
MOTOROLA