MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 526

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
to transmit, the BISYNC controller will fetch the data from memory and start transmitting the
message (after first transmitting the SYN1–SYN2 pair). The entire SYN1–SYN2 pair is
always transmitted, regardless of the programming of the SYNL bits in the GSMR.
When a BD’s data has been completely transmitted, L-bit is checked. If both the L-bit, and
transmit BCS bit are set in that BD, the BISYNC controller will append the CRC16/LRC. Sub-
sequently, the BISYNC controller writes the message status bits into the BD and clears the
R-bit. It will then start transmitting SYN1–SYN2 pairs or idles as programmed in the RTSM
bit in the GSMR. When the end of the current BD has been reached and the last bit is not
set (working in multibuffer mode), only the R-bit is cleared. In both cases, an interrupt is
issued according to the I-bit in the BD. By appropriately setting the I-bit in each BD, inter-
rupts can be generated after the transmission of each buffer, a specific buffer, or each block.
The BISYNC controller will then proceed to the next BD in the table.
If no additional buffers have been presented to the BISYNC controller for transmission, an
in-frame underrun is detected, and the BISYNC controller begins transmitting either SYNCs
or idles. If the BISYNC controller was in transparent mode, the BISYNC controller transmits
DLE-SYNC pairs.
Characters are included in the block check sequence (BCS) calculation on a per-buffer
basis. Each buffer can be independently programmed to be included or excluded from the
BCS calculation, and any characters to be excluded from the BCS calculation must reside
in a separate buffer. The BISYNC controller can reset the BCS generator before transmitting
a specific buffer. When functioning in transparent mode, the BISYNC controller automati-
cally inserts a DLE before transmitting a DLE character. In this case, only one DLE is used
in the calculation of the BCS.
7.10.20.3 BISYNC CHANNEL FRAME RECEPTION. Although the BISYNC receiver is
designed to work with almost no intervention from the CPU32+ core, it allows user interven-
tion on a per-byte basis if necessary. The BISYNC receiver can perform CRC16, longitudinal
redundancy check (LRC), or vertical redundancy check (VRC) checking, SYNC stripping in
normal mode, DLE-SYNC stripping and stripping of the first DLE in DLE-DLE pairs in trans-
parent mode, and control character recognition. A control character is discussed in
7.10.20.6 BISYNC Control Character Recognition.
When the CPU32+ core enables the BISYNC receiver, it will enter hunt mode. In this mode,
as data is shifted into the receiver shift register one bit at a time, the contents of the register
are compared to the contents of the SYN1–SYN2 fields in the data synchronization register.
If the two are not equal, the next bit is shifted in, and the comparison is repeated. When the
registers match, the hunt mode is terminated, and character assembly begins. The BISYNC
controller is now character synchronized and will perform SYNC stripping and message
reception. The BISYNC controller will revert to the hunt mode when it is issued the ENTER
HUNT MODE command, upon recognition of some error condition, or upon reception of an
appropriately defined control character.
When receiving data, the BISYNC controller updates the BCS bit (CR) in the BD for every
byte transferred. When the data buffer has been filled, the BISYNC controller clears the E-
bit in the BD and generates an interrupt if the I-bit in the BD is set. If the incoming data
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MC68360 USER’S MANUAL
MOTOROLA
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