MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 477

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Bits 10–9—Should be written with zeros.
A—Address
CHARSEND
7.10.16.11 SEND BREAK (TRANSMITTER). A break is an all-zeros character without a
stop bit(s). A break is sent by issuing the STOP TRANSMIT command. The UART com-
pletes transmission of any outstanding data, sends a programmable number of break char-
acters according to the break count register, and then reverts to idle or sends data if the
RESTART TRANSMIT command was given before completion. At the completion of the
break code, the transmitter sends at least one high bit before transmitting any data to guar-
antee recognition of a valid start bit.
The break characters do not preempt characters already in the transmit FIFO. This means
that the break character may not be transmitted for 8 character times (SCC1) or 4 character
times (SCC2, SCC3, and SCC4). To reduce this latency, the TFL bit in the GSMR should be
set to decrease the FIFO size to one character prior to enabling the SCC transmitter.
7.10.16.12 SENDING A PREAMBLE (TRANSMITTER). A preamble sequence gives the
programmer a convenient way of ensuring that the line goes idle before starting a new mes-
sage. The preamble sequence length is constructed of consecutive ones of one character
length. If the preamble bit in a BD is set, the SCC will send a preamble sequence before
transmitting that data buffer. Example: for 8 data bits, no parity, 1 stop bit, and 1 start bit, a
preamble of 10 ones would be sent before the first character in the buffer.
7.10.16.13 FRACTIONAL STOP BITS (TRANSMITTER). The asynchronous UART trans-
mitter can be programmed to transmit fractional stop bits. Four bits in the SCC data synchro-
nization register (DSR) are used to program the length of the last stop bit transmitted. These
DSR bits may be modified at any time. If two stop bits are transmitted, only the second one
is affected. Idle characters are always transmitted as full-length characters.
MOTOROLA
When working in a multidrop configuration, the user should include the address bit in this
position.
This value contains the character to be transmitted. Any 5-, 6-, 7-, or 8-bit character value
may be transmitted in accordance with the UART’s configuration. The character should
comprise the LSBs of CHARSEND. This value may be modified only while the REA bit is
cleared.
15
0
14
13
FSB
12
Freescale Semiconductor, Inc.
11
For More Information On This Product,
10
1
MC68360 USER’S MANUAL
Go to: www.freescale.com
1
9
8
0
0
7
Serial Communication Controllers (SCCs)
6
1
5
1
4
1
3
1
1
2
1
1
7-153
0
0