MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 363

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
IDMA Channels
For the single buffer mode, STR is cleared automatically when the BCR reaches zero or
when DONEx is asserted externally. For the other buffer handling modes see 7.6.4.8.2 Auto
Buffer Mode Termination. and 7.6.4.8.3 Buffer Chaining Mode Termination. The STR is
cleared in all modes if the IDMA cycle is terminated by a bus error.
Channel transfer operation may be suspended at any time by clearing STR in software. In
response, any operand transfer in progress will be completed, and the bus will be released.
No further bus cycles will be started while STR remains cleared. During this time, the
CPU32+ core may access IDMA internal registers to determine channel status or to alter
operation. When STR is set again, if a transfer request is pending, the IDMA will arbitrate
for the bus and continue normal operation.
Interrupts from the IDMA are sent to the interrupt controller. In the interrupt handler, the
unmasked bits in the CSR should be cleared (by writing them with a one) to negate the inter-
rupt request to the CPM interrupt controller.
7.6.4.4 REQUESTING IDMA TRANSFERS. Once the IDMA has been started, the transfers
can be requested to the IDMA.
IDMA transfers may be initiated by either internally or externally generated requests. Inter-
nally generated requests can be initiated by setting STR in the CMR or, in auto buffer and
buffer chaining modes, by also setting RCI in the CMR and preparing a data buffer to the
RISC controller. Externally generated transfers are those requested by an external device
using DREQx in conjunction with the activation of STR.
7.6.4.4.1 Internal Maximum Rate. The first method of internal request generation is a non-
stop transfer until the transfer count is exhausted. If this method is chosen, the IDMA will
arbitrate for the bus and begin transferring data after STR is set and the IDMA becomes the
bus master. During each access to the device (determined by the ECO bit in the CMR), the
IDMA will assert DACKx to indicate to the device that it is being serviced. If no exception
occurs, all operands in the data block will be transferred in one burst with the IDMA using
100% of the available bus bandwidth (unless a higher priority bus master requests the bus
or a higher priority interrupt requests service). See 7.6.2.2 Channel Mode Register (CMR)
for more detail.
7.6.4.4.2 Internal Limited Rate. To guarantee that the IDMA will not use all the available
system bus bandwidth during a transfer, internal requests can be limited to the amount of
bus bandwidth allocated to the IDMA. Programming the REQG bits to internal limited rate
and the BT bits to determine the percentage of bandwidth achieves this result. The options
are 12.5%, 25%, 50%, or 75% of the bus. As soon as STR is set, the IDMA module arbitrates
for the bus and begins to transfer data when it becomes bus master. During each access to
the device (determined by the ECO bit in the CMR), the IDMA will assert DACKx to indicate
that it is being serviced. If no exception occurs, transfers will continue normally, but the
IDMA will not exceed the percentage of bus bandwidth programmed into the control register.
The percentage is calculated over each ensuing 1024 internal clock cycle period.
For example, if 12.5% is chosen, the IDMA will attempt to use the bus for the first 128 clocks
of each 1024 clock cycle period. However, because of other bus masters or higher priority
MOTOROLA
MC68360 USER’S MANUAL
7-39
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