MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 563
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MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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12
12-38
The processor also halts if it receives a bus error or address error during the
vector table read operations or the prefetch for the first instruction after an
conditions, which include MMU address translation cache miss, reset, bus
error, address error, spurious interrupt, autovectored interrupt, and F-line
STATUS to assert for three clock cycles to indicate that normal instruction
case since these exceptions are processed immediately, not just at instruction
Figure 12-22 shows the assertion of STATUS, indicating that the processor
has halted due to a double bus fault. Once a bus error has occurred, any
additional bus error exception occurring before the execution of the first
instruction of the bus error handler routine constitutes a double bus fault.
external reset. STATUS remains asserted until the processor is reset.
Figure 12-21 illustrates the assertion of the STATUS signal for other exception
instruction when no coprocessor responds. Exception processing causes
processing has stopped. Instruction boundaries cannot be determined in this
boundaries.
I N STRUCTI O N
BOUNDARI E S
STATUS
REFI L L
STATUS
REFI L L
CLK
CLK
Figure 12-20. Trace or Interrupt Exception
Figure 12-21. Other Exceptions
M068030 USER'S MANUAL
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