MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 430

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10.4.9 E v a l u a t e Effective A d d r e s s and Transfer Data P r i m i t i v e
MOTOROLA
The evaluate effective address and transfer data primitive transfers an op-
the evaluate effective address and transfer data primitive.
erand between the coprocessor and the effective address specified in the
ceprocessor instruction operation word. This primitive applies to general
category instructions. If the coprocessor issues this primitive during the ex-
ecution of a conditional category instruction, the main processor initiates
I cA I Pc i °" I '
This primitive uses the CA, PC, and DR bits as previously described.
The valid effective address field (bits [8-10]) of the primitive format specifies
the valid effective address categories for this primitive. If the effective address
specified in the instruction operation word is not a member of the class
specified by bits E8-10], the main processor aborts the coprocessor instruc-
tion by writing an abort mask (refer to 10.3.2 Control CIR) to the control CIR
valid effective address field encodings.
protocol violation exception processing. Figure 10-29 shows the format of
Figure 10-29. Evaluate Effective Address and Transfer Data Primitive Format
and by initiating F-line emulation exception processing. Table 10-4 lists the
15
14
13
12
11
I 0 I vA,10E~
Field
000
001
011
010
100
110
111
101
MC68030 USER'S MANUAL
Table 10-4. Valid Effective
10
Control Alterable
Alterable
Any Effective Address
Data Alterable
Memory Alterable
Control
Data
Memory
Address Codes
(No Restriction)
8
I
Category
7
,ENOT,
10-43
0
I
lo