MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 536

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

M O T O R O L A
12.4 M E M O R Y
The PAL equations and circuits presented here are not intended to be the
optimal implementation for every system. Depending on the CPU's clock
frequency, memory access times, and system architecture, different circuits
The MC68030 is capable of running three types of external bus cycles as
determined by the cyc!e termination and handshake signals (refer to SECTION
7 BUS OPERATION). These three types of bus cycles are:
may be required.
3. Burst operation cycles, terminated by the STERM and CBACK signals,
2. Synchronous cycles, terminated by the STERM signal, have a minimum
1. Asynchronous cycles, terminated by the DSACKx signals, have a min-
W o r d
T h r e e Byte
Byte
L o n g W o r d
Transfer
Table 12-1. Data Bus Activity for Byte, Word, and Long-Word Ports
transferred.
to four long words (16 bytes) are transferred.
duration of two processor clock periods in which up to four bytes are
imum duration of three processor clock periods in which up to four
bytes are transferred.
have a duration of as little as five processor clock periods in which up
Size
INTERFACE
S l Z l
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SlZO
- 0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
M C 6 8 0 3 0
I
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
U S E R ' S
A0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
M A N U A L
D31-D24
Byte (B) - Word (W) - Long-Word (L) Ports
B W
B W L
B W
B W L
B W
B W L
B W
B W L
B
B
B
B
B
B
B
B
Data Bus Active Sections
D23-D16
- -
W L
W
W L
W
W
W L
W
W
W L
W
W
- -
W L
W L
W L
D15-D8
- -
- -
- -
- -
- -
- -
- -
L
L
L
L
L
L
L
L
L
- -
- -
- -
- -
- -
- -
L
L
L
L
L
L
L
L
L
L
D7-D0
12-11
12