MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 252
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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7.5.3
MOTOROLA
When HALT is asserted and BERR is not asserted, the MC68030 halts external
timing requirements provides a single-step (bus cycle to bus cycle) operation.
The HALT signal affects external bus cycles only; thus, a program that resides
the data cache) may continue executing, unaffected by the HALT signal.
a bus cycle. Negating and reasserting HALT in accordance with the correct
in the instruction cache and performs no data writes (or reads that miss in
bus activity at the next bus cycle boundary. HALT by itself does not terminate
Halt Operation
SIZ0-SIZ1 : : ~
FC0-FC2
A0-A3I
gO-O3~
STERM
RER- - ~ --/------k
"~ --E--------k
R/W . . _ j /
~ - - k _ /
CLK
SO S]
ETRY SIGNALED r
Figure 7-55, Synchronous Late Retry
$2
MC68030 USER'S MANUAL
$3
-
/
•
HALT
/
, = j - -
k _ _ /
k---/.
SO Sl
RETRY CYCLE
$2
$3
7-91
7
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