MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 322

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
WP
CI
This bit is automatically set by the processor when a descriptor is accessed
set, for an address to which access is denied at another level of the tree.
This bit provides write protection. The states of all WP bits encountered
during a table search are logically ORed, and the result is copied to the
ATC entry at the end of a table search for a logical address. During a table
search for a PTEST instruction, the processor copies this result into the
allow the logical address space mapped by that descriptor to be written
stricted at some other level of the translation tree).
This bit is set to inhibit caching of items within this page by the on-chip
signal by the MC68030 for bus cycles accessing items within this page.
in which the U bit is clear except after a supervisor violation is detected.
In a page descriptor table, this bit is set to indicate that the page corre-
sponding to the descriptor has been accessed. In a pointer table, this bit
is set to indicate that the pointer has been accessed by the MC68030 as
part of a table search. Note that a pointer may be fetched, and its U bit
Updates of the U bit are performed before the MC68030 allows a page to
be accessed. The processor never clears this bit.
MMU status register (MMUSR). When WP is set, the MC68030 does not
by any program (i.e., this protection is absolute). If the WP bit is clear, the
MC68030 allows write accesses using this descriptor (unless access is re-
instruction and data caches and, also, to cause the assertion of the CLOUT
$3
$2
VALID 8 BYTE
This code specifies that the next table to be accessed contains
table (bottom level of an address translation tree), this code iden-
tifies an indirect descriptor that points to a long-format page de-
scriptor.
VALID 4 BYTE
This code specifies that the next table to be accessed contains
short-format descriptors. The MC68030 multiplies the index for the
descriptors must be long-word aligned.) When used in a page table
descriptor that points to a short-format page descriptor.
descriptors must be quad-word aligned.) When used in a page
next table by four to access the next descriptor. (Short-format
(bottom level of an translation tree), this code identifies an indirect
long-format descriptors. The MC68030 multiplies the index for the
next table by eight to access the next descriptor. (Long-format
MC68030 USER'S MANUAL
9-21
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