MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 236
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MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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7.5 B U S E X C E P T I O N
l
l
MOTOROLA
2) SET FUNCTION CODE TO cPu SPACE
3) PLACE CPU SPACE TYPE 0 ON A16-A1R
4) BLADE BREAKPOINT NDMBEB ON A2-At~
2) CON~NUE PROCESSING
1} SET R/WTO READ
5) SET SIZE TO WORD
6) ASSERT ADDRESS STROBE (~) AND DATA STROBE (D-S}
IF DSACKx OR STERM ASSERTED:
IF BERR ASSERTED:
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
1) PtACE LATCHED DATA IN INSTRUCTION PIPELINE
2) NEGATE AS AND OS
3) G0 TO@
21DOTD®
1) LATCH DATA
1) NEGATE AS AND OS
The MC68030 bus architecture requires assertion of either DSACKx or STERM
from an external device to signal that a bus cycle is complete. DSACKx,
STERM, or AVEC is not asserted if:
to enter exception processing for the error condition.
External circuitry can provide BERR when no device responds by asserting
processor asserts AS. This allows the cycle to terminate and the processor
The M M U can also detect an internal bus error. This occurs when the pro-
cessor attempts to access an address in a protected area of memory (a user
program attempts to access supervisor data, for example) or after the M M U
DSACKx, STERM, or AVEC within an appropriate period of time after the
receives a bus error while searching the address table for an address trans-
lation description.
• The external device does not respond.
• No interrupt vector is provided.
• Various other application-dependent errors occur.
BREAKPOINT ACKNOWLEDGE
PROCESSOR
®
Figure 7-46. Breakpoint Operation Flow
C O N T R O L
MC68030 USER'S MANUAL
or
J
, .
I-
C Y C L E S
2= ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx)
! ~ ASSERT BUS ERROR (BERR} TO INITIATE EXCEPTION PROCESSING
, PLACE REPLACEMENT OPCODE ON DATA BUS
OR SYNCHRONOUS TERMINATION (STERM)
SLAVE NEGATES DSACKx. STERM OR BERR
EXTERNAl DEVICE
-
O R
I
-
7-75
7
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