MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 144
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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~
MOTOROLA
I
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
The data cache on the MC68030 is a writethrough cache. When a hit occurs
the write is aborted, the corresponding entry is invalidated, and a bus error
to external memory, the cache contains the new value even if the external
though this should not have any adverse consequences. Refer to 7.6 BUS
on a write cycle, the data is written both to the cache and to external memory
(provided the M M U validates the access), regardless of the operand size and
even if the cache is frozen. If the M M U determines that the access is invalid,
exception is taken. Since the write to the cache completes before the write
write terminates in a bus error. The value in the data cache might be used
SYNCHRONIZATION for the details of bus synchronization.
by another instruction before the external write cycle has completed, al-
IA..;A A A A A A A A A A A A A A A A a : A a A A A l
3 , . . 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0
1...3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7
1 OF 16 L ~
SELECT l
~61
Figure 6-3. On-Chip Data Cache Organization
I
MC68030 USER'S MANUAL
TAD
;
V V V V
l )
•
j
JL_J
H
0
~
i
LINE HIT
- - D
O
VALID
I',S~X
i
i I I
LONG WORO
3 0 0 0 0
111
SELECT
I
I
3 2 I 0
•
,L
ENTRY HIT
•
ACCESS ADDRESS
,L
Q
o
T
L ~ "
~ CACHE CONTROL LOGIC
DATA FROM DATA CACHE
DATA BUS
DATA TO
EXECUTION UNIT
6-7
6
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