MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 215

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Im
7.3.6 Synchronous Read-Modify-Write Cycle
7-54
State 3
A synchronous read-modify-write operation differs from an asynchronous
write cycles and in the use of CLK instead of DS latching data in the write
cycle. Like the asynchronous operation, the synchronous read-modify-write
operation is indivisible. Although the operation is synchronous, the burst
Timing for the cycle is shown in Figure 7-36.
State 2
read-modify-write operation only in the terminating signal of the read and
mode is never used during read-modify-write cycles.
Figure 7-35 is a flowchart of the synchronous read-modify-write operation.
The processor negates AS (and DS, if necessary) during $3. It holds the
address and data valid during $3 to simplify memory interfaces.
SIZ0-SlZl, FC0-FC2, and DBEN also remain valid throughout $3.
The addressed device must negate STERM within two clock periods after
selected device uses R/W, CLK, SIZ0-SIZ1, and A0-A1 to latch data from
the appropriate section(s) of the data bus (D24-D31, D16-D23, D8-D15,
and D0-D7). SIZ0-SIZ1 and A0-A1 select the data bus sections. The device
asserts STERM when it has successfully stored the data. If the device does
until it is recognized. The processor asserts DS at the end of $2 if wait
states are inserted. For zero-wait-state synchronous write cycles, DS is not
asserted.
asserting it, or the processor may use STERM for the next bus cycle.
During $2, the processor places the data to be written onto D0-D31. The
not assert STERM by the rising edge of $2, the processor inserts wait states
MC68030 USER'S MANUAL
MOTOROLA
R/W,