MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 33

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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1.2 M C 6 8 0 3 0 E X T E N S I O N S TO THE M 6 8 0 0 0 FAMILY
1.3 P R O G R A M M I N G M OD EL
two-clock cycle synchronous mode and burst mode accesses that can transfer
Additional signals support emulation and system analysis. External debug
This status and control information allows external debugging equipment to
trace the MC68030 activity and interact nonintrusively with the MC68030 to
The programming model of the MC68030 consists of two groups of registers:
the data operand required by an instruction is already in the data cache.
accessed in a single clock cycle. In addition, the bus controller provides a
data in as little as one clock per long word.
The MC68030 enhanced microprocessor contains an on-chip MMU that al-
caches, and the bus controller.
equipment can disable the on-chip caches and the MMU to freeze the MC68030
cates:
effectively reduce system debug effort.
the user model and the supervisor model. This corresponds to the user and
supervisor privilege levels. User programs executing at the user privilege
supervisor level uses the control registers of the supervisor level to perform
may be stored in the on-chip cache, where it is available for subsequent
accesses. The data cache reduces the number of external bus cycles when
Performance is enhanced further because the on-chip caches can be internally
lows address translation to operate in parallel with the CPU core, the internal
internal state during breakpoint processing. In addition, the MC68030 indi-
level use the registers of the user model. System software executing at the
supervisor functions.
In addition to the on-chip instruction cache present in the MC68020, the
MC68030 has an internal data cache. Data that is accessed during read cycles
2. Instruction boundaries
3. Pending trace or interrupt processing
4. Exception processing
5. Halt conditions
1. The start of a refill of the instruction pipe
MC68030 USER'S MANUAL
MOTOROLA