MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 96

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

3.2.8 P r o g r a m Control Instructions
M O T O R O L A
" Letters
A set of subroutine call and return instructions and conditiona and uncon-
ditional branch instructions perform program control operations. The no
operation instruction (NOP) may be used to force synchronization of the
internal pipelines. Table 3-8 summarizes these instructions.
JMP
JSR
Bcc
DBcc
Scc
BSR
NOP
RTD
RTR
RTS
BRA
~Not applicable to the Bcc or cpBcc instructions.
CC
LS - - Lower or same
CS - - C a r r y set
LT
EQ--Equal
MI
F - - Never true "x"
NE
Instruction
cc in the integer instruction mnemonics Bcc, DBcc, and Scc specify testing one of the following conditions:
Carry clear
Minus
Not equal
Less than
I
Operand Syntax I Operand Size I
Dn,<label>
<label>
<label>
<label>
# < d >
<ea>
<ea>
<ea>
none
none
none
Table 3-8. Program Control Operations
M C 6 8 0 3 0 USER'S
Integer and Floating-Point Conditional
I
I
8,16,32
8,16,32
8,16,32
none
none
none
none
none
16
16
8
GE
T
VC - - Overflow clear
VS - - O v e r f l o w set
PL
G T - - Greater than
HI --Higher
LE
Unconditional
- - A l w a y s true ~+
Returns
Greater or equal
Plus
Less or equal
/
.L f condition true, then PC+d D PC
I,
I i f condition true, then l's J destination:
|
PC+d 0 PC
S P - 4 $ SP; PC B (SP); PC+d i) PC
destination 0 PC
S P - 4 i SP: PC J ~SP); destination D PC
PC+2 * PC
(SP) 0 PC; S P + 4 + d ~, SP
(SP) ~ CCR; SP+2 $SP; (SP) $ PC; SP-~4 I) SP
f condition false, then Dn - 1 • Dn
SP $PC; SP+41SP
M A N U A L
if Dn~ - 1 , then PC+d i PC
else O's 0 destination
Operation
3-11
3