MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 414

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10.2.3.4 COPROCESSOR CONTEXT RESTORE INSTRUCTION.
10.2.3.4.1 Format.
MOTOROLA
tion and the coprocessor is unable to support the suspension of these two
forces a coprocessor to terminate any current operations and to restore a
former state. During the execution of a cpRESTORE instruction, the copro-
I
the coprocessor identification code in bits [9-11] and an M68000 effective
following the first word in the cpRESTORE instruction format. These words
coprocessor can return the invalid format word, however, if a cpSAVE is
cessor context restore instruction category includes one instruction. The co-
cessor can communicate status information to the main processor by placing
format codes in the restore CIR.
The first word of the instruction is the F-line operation word, which contains
cessor context is stored. The effective address is that of the coprocessor
format word that applies to the context to be restored to the coprocessor.
The instruction can include as many as five effective address extension words
contain any additional information required to calculate the effective address
specified by bits [0-5] of the operation word.
All memory addressing modes except the predecrement addressing mode
are valid. Invalid effective address encodings cause the MC68030 to initiate
EXCEPTIONS).
does not include this case since a coprocessor usually returns either a not
ready or a valid format code in the context of the cpSAVE instruction. The
initiated while the coprocessor is executing a cpSAVE or cpRESTORE instruc-
instructions.
processor context restore instruction, denoted by the cpRESTORE mnemonic,
Figure 10-17. Coprocessor Context Restore Instruction Format (cpRESTORE)
addressing code in bits [0-5]. The effective address encoded in the cp-
RESTORE instruction is the starting address in memory where the copro-
F-line emulator exception processing (refer to 10.5.2.2 F-LINE EMULATOR
15
1
14
1
13
1
Figure 10-17 shows the format of the cpRESTORE instruction.
12
1
EFFECTI V E ADDRESS EXTENSION WORDS (0-5 WORDS)
11
MC68030 USER'S
CpID
9
1
8
MANUAL
O
7
1
6
5
EFFECTI V E ADDRESS
The M68000 copro-
10-27
0
1 0