MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 397
MC68030FE25C
Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68030FE25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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10-10
10.2.1.1 FORMAT.
A coprocessor general type instruction consists of at least two words. The
The CplD field of the F-line operation code is used during the coprocessor
CODING SUMMARY). During the execution of a cpGEN instruction, the co-
tion. Using the effective address specifier field of the F-line operation code,
the processor then determines the effective addressing mode. If a coproces-
The second word of the general-type instruction is the coprocessor command
word. The main processor writes this command word to the command CIR
to initiate execution of the instruction by the coprocessor.
The mnemonic cpGEN is a generic mnemonic used in this discussion for all
general instructions. The mnemonic of a specific general instruction usually
suggests the type of operation it performs and the coprocessor to which it
applies. The actual mnemonic and syntax used to represent a coprocessor
generates the object code.
first word of the instruction is an F-line operation code (bits [15:12] = 1111 ).
access to indicate which of the coprocessors in the system executes the
10.1.4.2 PROCESSOR-COPROCESSOR INTERFACE), the processor places the
CplD on address lines A13-A15.
Bits [8:6] =000 indicate that the instruction is in the general instruction cat-
egory. Bits 0-5 of the F-line operation code sometimes encodes a standard
processor can use a coprocessor response primitive to request that the
sor never requests effective address calculation, bits 0-5 can have any value
instruction is determined by the syntax of the assembler or compiler that
instruction. During accesses to the coprocessor interface registers (refer to
M68000 effective address specifier (refer to 2.5 EFFECTIVE ADDRESS EN-
MC68030 perform an effective address calculation necessary for that instruc-
(don't cares).
15
I 1
14
Figure 10-6. Coprocessor General Instruction Format (cpGEN)
I
OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR-DEFI N ED EXTENSION WORDS
13
Figure 10-6 shows the format of a general type instruction.
12
I
I
11
MC68030 USER'S MANUAL
cp,0
COPROCESSOR COMMAND
9
I 0 I 0 I °
8
7
6
5
I EFFECT,VEA00RESS
MOTOROLA
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