MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 540

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
certain a m o u n t of t i m e later as defined by specification #31. With a 16.67-
the current bus cycle. In true asynchronous operations, such as accesses to
the actual clock frequency).
During asynchronous bus cycles, DSACK1 and DSACK0 are used to terminate
peripherals operating at a different clock frequency, either or both signals
m a y be asserted w i t h o u t regard to the clock, and then data must be valid a
MHz processor, this t i m e is 50 ns after DSACKx asserts; with a 20.0-MHz
processor, this t i m e is 43 ns after DSACK asserts (both numbers vary with
DSACKO/DSACK1
Parameter
BERR,
NOTE: This diagram illustrates access time calculations only. ~
A0-A31
DO-D31
STERM
HALT
CLK
never be asserted together during the same bus cycle.
Address Valid to DSACKx Asserted
Address Strobe Asserted to DSACKx Asserted
Address Valid to STERM Asserted
Address Strobe Asserted to STERM Asserted
Address Valid to BERn/HALT Asserted
Address Strobe Asserted to BERR/HALT Asserted
Address Valid to Data Valid
Address Strobe Asserted to Data Valid
Figure 12-8. Access Time Computation Diagram
SO
MC68030 USER'S MANUAL
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Description
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~-~ C -*Ira, - -
/
I
~
g-~
h~,
- _ _ /
tAVBHL
tSABHL
System
tAVDV
tSADV
tAVDL
tSADL
tAVSL
tSASL
and STERM should
/
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x
SO
Equation
12-1
12-5
12-6
12-7
12-2
12-3
12-4
12-8
12-15
12