MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 424

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10:4.4 Null Primitive
I cAI P° I ° I ° I
The busy primitive should only be used in response to a write to the command
The MC68030 responds to the busy primitive differently in a special case that
can occur during a breakpoint operation (refer to 8.1.12 Multiple Exceptions).
This special case occurs when a breakpoint acknowledge cycle initiates a
three conditions are met, the processor re-executes the breakpoint acknowl-
The null coprocessor response primitive communicates coprocessor status
the general and conditional categories. Figure 10-24 shows the format of the
This primitive uses the CA and PC bits as previously described.
or condition CIR. It should be the first primitive returned after the main
processor attempts to initiate a general or conditional category instruction.
In particular, the busy primitive should not be issued after program-visible
resources have been altered by the instruction. (Program-visible resources
include coprocessor and main processor program-visible registers and op-
erands in memory, but not the scanPC.) The restart of an instruction after it
has altered program-visible resources causes those resources to have in-
consistent values when the processor reinitiates the instruction.
coprocessor F-line instruction, the coprocessor returns the busy primitive in
response to the instruction initiation, and an interrupt is pending. When these
edge cycle after the interrupt exception processing has been completed. A
design that uses a breakpoint to monitor the number of passes through a
loop by incrementing or decrementing a counter may not work correctly
under these conditions. This special case may cause several breakpoint ac-
knowledge cycles to be executed during a single pass through a loop.
information to the main processor. This primitive applies to instructions in
null primitive.
Bit [8], the IA bit,
determines whether the MC68030 services pending interrupts prior to re-
reading the response ClR after receiving a null primitive. Interrupts are al-
lowed when the IA bit is set.
T5
14
13
12
specifies
Figure 10-24. Null Primitive Format
11
,
MC68030 USER'S MANUAL
I o I o I,AIo
10
the interrupts allowed optional operation. This bit
9
8
7
I o I o I o I o I o
6
5
4
3
2
I PFI TF I
1
10-37
0
1(