MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 437

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MC68030FE25C

Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68030FE25C

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
10
10.4.13 Transfer Single Main Processor Register Primitive
10.4.14 Transfer Main Processor Control Register Primitive
10-50
This primitive uses the CA, PC, and DR bits as previously described. If the
The transfer single main processor register primitive transfers an operand
tions. Figure 10-33 shows the format of the transfer single main processor
coprocessor issues this primitive with CA=O during a conditional category
cessing.
data register. D/A=O indicates a data register, and D/A= 1 indicates an ad-
dress register. Bits [2-0] contain the register number.
operand from the operand CIR and transfers it to the specified data or address
The transfer main processor control register primitive transfers a long-word
This primitive uses the CA, PC, and DR bits as previously described. If the
processor. This primitive applies to general and conditional category instruc-
instruction, the main processor initiates protocol violation exception pro-
Bit [3], the D/A bit, specifies whether the primitive transfers an address or
If DR=O, the main processor writes the long-word operand in the specified
register to the operand CIR. If DR = 1, the main processor reads a long-word
register.
operand between one of its control registers and the coprocessor. This pri-
mitive applies to general and conditional category instructions. Figure 10-34
shows the format of the transfer main processor control register primitive.
coprocessor issues this primitive with C A = 0 during a conditional category
cessing.
between one of the main processor's data or address registers and the co-
register primitive.
instruction, the main processor initiates protocol violation
CA
15
Figure 10-33. Transfer Single Main Processor Register Primitive Format
PC
14
DR
13
i2
0
11
1
MC68030 USER'S MANUAL
10
1
9
0
8
0
7
0
6
0
5
0
4
0 D/A
3
exception
REGISTER /
MOTOROLA
2
pro-
J
0

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