MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 256

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.6 BUS SYNCHRONIZATION
MOTOROLA
The MC68030 overlaps instruction execution; that is, during bus activity for
tivity, the NOP instruction can be used. The NOP instruction forces instruction
An example of the use of the NOP instruction for this purpose is the case of
that is written with the conditional assertion of BERR. If the data cache is
the external write cycle completes. Since the MC68030 cannot process the
from executing until the external cycle completes, a NOP instruction can be
tion processing proceeds immediately after the write before subsequent in-
validity of write cycles before they proceed to the data cache and are executed
Thus, there is no danger in subsequent instructions using erroneous data
A bus synchronization example is given in Figure 7-58.
one instruction, instructions that do not use the external bus can be executed.
Due to the independent operation of the on-chip caches relative to the op-
eration of the bus controller, many subsequent instructions can be executed,
resulting in seemingly nonsequential instruction execution. When this is not
desired and the system depends on sequential execution following bus ac-
and bus synchronization in that it freezes instruction execution until all pend-
ing bus cycles have completed.
a write operation of control information to an external register, where the
external hardware attempts to control program execution based on the data
enabled and the write cycle results in a hit in the data cache, the cache is
updated. That data, in turn, may be used in a subsequent instruction before
bus error until the end of the bus cycle, the external hardware has not suc-
cessfully interrupted program execution. To prevent a subsequent instruction
structions are executed. T h i s s an irregular situation, and the use of the NOP
instruction for this purpose is not required by most systems.
externally, the MC68030 is guaranteed to write correct data to the cache.
from the cache before an external bus error signals an error.
inserted after the instruction causing the write. In this case, bus error excep-
Note that even in a system with error detection/correction circuitry, the NOP
is not required for this synchronization. Since the MMU always checks the
MC68030 USER'S MANUAL
7-95