MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 305

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MC68030FE25C

Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68030FE25C

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
9
9-4
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1
I
63
31
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31
with all tag entries in the ATC. When the access address and function code
the ATC outputs the corresponding physical address to the bus controller,
The ATC in the MMU is a fully associative cache that stores 22 logical-to-
the logical address and function code internally supplied by the processor
which continues the external bus cycle. Function codes are routed to the bus
controller unmodified.
When the ATC does not contain the translation for a logical address (a miss
tables in memory for the correct translation. If the table search completes
the physical address for the access, allowing the bus controller to retry the
physical address translations and associated page information. It compares
matches a tag in the ATC (a hit occurs) and no access violation is detected,
Each ATC entry contains a logical address, a physical address, and status
bits. Among the status bits are the write protect and cache inhibit bits.
occurs) and an external bus cycle is required, the MMU aborts the access
and causes the processor to initiate bus cycles that search the translation
without any errors, the MMU stores the translation in the ATC and provides
original bus cycle.
Figure 9-2. MMU Programming Model
TRANSPARENT TRANSLATION 0
TRANSPARENT TRANSLATION 1
MC68030 USER'S MANUAL
TRANSLATION CONTROL
SUPERVISOR R00T
CPU
POINTER
POINTER
I
ROOT
15
MMU STATUS (MMUSR)
32
32
0
0
0
0
0
0
I
I
I
I
I
I
~__ STATUS
MOTOROLA
AODRESS
TRANSLATION
CONTROL
REGI S TERS
INFORMATION
REGI S TER

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