MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 47

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

F—Freeze Cache
E—Enable Cache
4.3.2 Cache Address Register (CAAR)
The format of the 32-bit CAAR is shown in Figure 4-3.
Bits 31–8, 1, and 0—Reserved
Index Field
4–4
31
The F-bit is set to freeze the instruction cache. When the F-bit is set and a cache miss
occurs, the entry (or line) is not replaced. When the F-bit is clear, a cache miss causes
the entry (or line) to be filled. A reset operation clears the F-bit.
The E-bit is set to enable the instruction cache. When it is clear, the instruction cache is
disabled. A reset operation clears the E-bit. The supervisor normally enables the
instruction cache, but it can clear the E-bit for system debugging or emulation, as
required. Disabling the instruction cache does not flush the entries. If the cache is
reenabled, the previously valid entries remain valid and may be used.
These bits are reserved for use by Motorola.
The index field contains the address for the “clear cache entry” operations. The bits of
this field, which correspond to A7–A2, specify the index and a long word of a cache line.
Figure 4-3. Cache Address Register
RESERVED
M68020 USER’S MANUAL
8
7
INDEX
2
MOTOROLA
RESERVED
1
0