MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 262

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PAL16L8
BYTE_SELECT
MC68020/EC020 BYTE DATA SELECT GENERATION FOR 32-BIT PORTS, MAPPED AND UNMAPPED.
MOTOROLA INC., AUSTIN, TEXAS
INPUTS:
OUTPUTS:
!~UUDA
!~UMDA
!~LMDA
!~LLDA
!~UUDB
!~UMDB
!~LMDB
!~LLDB
9-8
DESCRIPTION : Byte select signals for writing. On reads, all byte selects are asserted if the respective memory block is addressed.
The input signal CPU prevents byte select assertion during CPU space cycles and is derived from NANDing FC1–FC0 or FC2–FC0.
The label (addressb) is a designer-selectable combination of address lines used to generate the proper address decode for the
system's memory bank. With the address lines given here, the decode block size is 256 Kbytes to 2 Mbytes. A similar address might
be included in the equations for UUDA , UMDA , etc. if the designer wishes them to be memory mapped also.
A0
~UUDA
= RW
+!A0 *!A1
+A0 *!A1
+!A1 *!SIZ0
+!A1 *SIZ1
;directly addressed, any size
+!A1 *!SIZ0 *!SIZ1
+!A1 *SIZ0 *SIZ1
+!A1 *A0 *!SIZ0
= RW
+A0 *A1
+A0 *SIZ0 *SIZ1
+!SIZ0 *!SIZ1
+A1 *SIZ1
= RW *!~CPU * (addressb)
+!A0 *!A1 *!~CPU * (addressb)
+ A0 *!A1 *!~CPU * (addressb)
+!A1 *!SIZ0 *!~CPU * (addressb)
+!A1 *SIZ1 *!~CPU * (addressb)
=RW *!~CPU * (addressb)
+!A0 * A1 *!~CPU * (addressb)
+!A1 *!SIZ0 *!SIZ1 *!~CPU * (addressb)
+!A1 * SIZ0 * SIZ1 *!~CPU * (addressb)
+!A1 * A0 *!SIZ0 *!~CPU * (addressb)
=RW *!~CPU * (addressb)
+A0 * A1 *!~CPU * (addressb)
+ A0 * SIZ0 * SIZ1 *!~CPU * (addressb)
+!SIZ0 *!SIZ1 *!~CPU * (addressb)
+A1 * SIZ1 *!~CPU * (addressb)
= RW
= RW
= RW *!~CPU * (addressb)
Figure 9-6. MC68020/EC020 Byte Select PAL Equations
A1
~UMDA
SIZ0
SIZ1
~LMDA
M68020 USER’S MANUAL
RW
~LLDA
A18
;enable upper byte on read of 32-bit port
;directly addressed, any size
;even word aligned, size word or long word
;even word aligned, size is word or three byte
;even word aligned, size is three byte
;even word aligned, size is word or long word
;enable lower byte on read of 32-bit port
;size is long word, any address
;enable upper byte on read of 32-bit port
;directly addressed, any size
;directly addressed, any size
;even word aligned, size word or long word
;directly addressed, any size
;even word aligned, size is long word
;even word aligned, size is three byte
;even word aligned, size is word or long word
;directly addressed, any size
;odd byte alignment, three byte size
;size is long word, any address
;enable upper middle byte on read of 32-bit port
;directly addressed, any size
;enable lower middle byte on read of 32-bit port
;even word aligned, size is long word
;directly addressed, any size
;odd byte alignment, three byte size
;odd word aligned, word or three byte size
;enable upper middle byte on read of 32-bit port
;even word aligned, size is word or three byte
;enable lower middle byte on read of 32-bit port
;enable lower byte on read of 32-bit port
;odd word aligned, word or three byte size
~UUDA
A19
A20
~UMDB
A21
~LMDB
~CPU
~LLDB
MOTOROLA
+!A0 *A1