MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 137

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Priority level 7, the nonmaskable interrupt, is a special case. Level 7 interrupts cannot be
masked by the interrupt priority mask, and they are transition sensitive. The processor
recognizes an interrupt request each time the external interrupt request level changes
from some lower level to level 7, regardless of the value in the mask. Figure 6-3 shows
two examples of interrupt recognitions, one for level 6 and one for level 7. When the
MC68020/EC020 processes a level 6 interrupt, the interrupt priority mask is automatically
updated with a value of 6 before entering the handler routine so that subsequent level 6
interrupts are masked. Provided no instruction that lowers the mask value is executed, the
6-12
*
A—Asserted
N—Negated
Indicates that no interrupt is requested.
Interrupt Level
Requested
*
0
1
2
3
4
5
6
7
IPEND is not implemented in the MC68EC020.
*
Table 6-3. Interrupt Levels and Mask Values
OTHERWISE
Figure 6-2. Interrupt Pending Procedure
IPL2
N
N
N
N
A
A
A
A
Control Line Status
M68020 USER’S MANUAL
OR TRANSITION ON LEVEL 7
(MC68020 ASSERTS IPEND )
INTERRUPT LEVEL
SAMPLE AND SYNCH
INTERRUPT PENDING
IPL1
N
N
A
A
N
N
A
A
IPL2–IPL0
RESET
WITH STATUS REGISTER MASK)
(COMPARE INTERRUPT LEVEL
IPL0
N
A
N
A
N
A
N
A
I2–I0,
*
Required for Recognition
Interrupt Mask Value
N/A
1–0
2–0
3–0
4–0
5–0
7–0
0
*
MOTOROLA