MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 42

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

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2.8.4 Read-Modify-Write Cycle ( RMC )
This output signal identifies the bus cycle as part of an indivisible read-modify-write
operation. It remains asserted during all bus cycles of the read-modify-write operation to
indicate that bus ownership cannot be transferred.
2.9 EXCEPTION CONTROL SIGNALS
These signals are used by the MC68340 to recover from an exception.
2.9.1 Reset ( RESET )
This active-low, open-drain, bidirectional signal is used to initiate a system reset. An
external reset signal (as well as a reset from the SIM40) resets the MC68340 and all
external devices. A reset signal from the CPU32 (asserted as part of the RESET
instruction) resets external devices; the internal state of the CPU32 is not affected. The
on-chip modules are reset, except for the SIM40. However, the module configuration
register for each on-chip module is not altered. When asserted by the MC68340, this
signal is guaranteed to be asserted for a minimum of 512 clock cycles. Refer to Section 3
Bus Operation for a description of bus reset operation and Section 5 CPU32 for
information about the reset exception.
2.9.2 Halt ( HALT )
This active-low, open-drain, bidirectional signal is asserted to suspend external bus
activity, to request a retry when used with BERR , or to perform a single-step operation. As
an output, HALT indicates a double bus fault by the CPU32. Refer to Section 3 Bus
Operation for a description of the effects of HALT on bus operation.
2.9.3 Bus Error ( BERR )
This active-low input signal indicates that an invalid bus operation is being attempted or,
when used with HALT , that the processor should retry the current cycle. Refer to Section
3 Bus Operation for a description of the effects of BERR on bus operation.
2.10 CLOCK SIGNALS
These signals are used by the MC68340 for controlling or generating the system clocks.
See Section 4 System Integration Module for more information on the various clocking
methods and frequencies.
2.10.1 System Clock (CLKOUT)
This output signal is the system clock output and is used as the bus timing reference by
external devices. CLKOUT can be varied in frequency or slowed in low power stop mode
to conserve power.
2-8
MC68340 USER’S MANUAL
MOTOROLA
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