MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 377

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

An overview of the MC68340 implementation of IEEE 1149.1 is shown in Figure 9-1. The
MC68340 implementation includes a 16-state controller, a 3-bit instruction register, and
two test registers (a 1-bit bypass register and a 132-bit boundary scan register). This
implementation includes a dedicated TAP consisting of the following signals:
9.2 TAP CONTROLLER
The TAP controller is responsible for interpreting the sequence of logical values on the
TMS signal. It is a synchronous state machine that controls the operation of the JTAG
logic. The state machine is shown in Figure 9-2; the value shown adjacent to each arc
represents the value of the TMS signal sampled on the rising edge of the TCK signal. For
a description of the TAP controller states, please refer to the IEEE 1149.1 document.
9-2
TCK
TMS — a test mode select input (with an internal pullup resistor) that is sampled on
TDI
TDO — a three-state test data output that is actively driven in the shift-IR and shift-
TMS
TCK
TDI
— a test clock input to synchronize the test logic
— a test data input (with an internal pullup resistor) that is sampled on the
the rising edge of TCK to sequence the TAP controller's state machine
rising edge of TCK.
DR controller states. TDO changes on the falling edge of TCK.
CTLR
TAP
TEST DATA REGISTERS
132
Figure 9-1. Test Access Port Block Diagram
BYPASS
Freescale Semiconductor, Inc.
2
For More Information On This Product,
BOUNDARY SCAN REGISTER
3-BIT INSTRUCTION REGISTER
MC68340 USER’S MANUAL
Go to: www.freescale.com
(133 BITS)
DECODER
0
0
M
U
X
M
U
X
MOTOROLA
TDO