MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 165

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

5-28
Instruction
ILLEGAL
LPSTOP
MOVEA
MOVEC
MOVES
TRAPcc
RESET
TRAPV
MOVE
MOVE
STOP
BGND
BKPT
CHK2
TRAP
ANDI
EORI
ANDI
EORI
CHK
RTE
ORI
ORI
# data CCR
# data CCR
# data CCR
# data , SR
# data , SR
# data , SR
CCR, ea
Operand
USP, An
An, USP
SR, ea
ea , CCR
Rn, ea
Syntax
ea , SR
Rc, Rn
Rn, Rc
# data
# data
# data
# data
# data
ea , Rn
ea , Dn
ea , Rn
none
none
none
none
none
none
Table 5-11. System Control Operations
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Operand Size
Go to: www.freescale.com
Condition Code Register
8, 16, 32
8, 16, 32
16, 32
16, 32
none
none
none
none
none
none
none
none
none
16
16
16
16
32
32
32
32
16
16
16
16
8
8
8
Trap Generating
Privileged
Immediate Data
Immediate Data
Source
SR
USP
An
Rc
Rn
Rn
Source using SFC
Immediate Data V SR
Assert RESET line
(SP)
SP; restore stack according to format
Immediate Data
Immediate Data
STOP
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal
instruction.
If background mode enabled, then enter background
mode, else format/vector offset
PC
If Dn < 0 or Dn < (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
SSP – 2
SSP – 4
SSP – 2
llegal instruction vector address
SSP – 2
SSP – 4
vector address
If cc true, then TRAP exception
If V set, then overflow TRAP exception
Immediate Data
Immediate Data
Source
CCR
Immediate Data V CCR
Rc
USP
Rn
Destination using DFC
Destination
– (SSP); SR
An
SR; SP + 2
Destination
SR
CCR
SSP; vector offset
SSP; PC
SSP; SR
SSP; format/vector offset
SSP; PC
PC
CCR
SR
CCR
SR
SR; interrupt mask
SR; STOP
Operation
Rn
– (SSP); (vector)
SP; (SP)
(SSP);
(SSP);
(SSP); SR
SR
SR
SR
CCR
CCR
CCR
(SSP);
– (SSP);
PC; SP + 4
PC
(SSP);
(SSP);
EBI;
PC
MOTOROLA