MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 173

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

5.3.4.5 Table Example 5: Surface Interpolations. The various forms of table can be
used to perform surface (3D) TBLs. However, since the calculation must be split into a
series of 2D TBLs, the possibility of losing precision in the intermediate results is possible.
The following code sequence, incorporating both TBLS and TBLSN, eliminates this
possibility.
Before execution of this code sequence, Dx must contain fraction and entry numbers for
the two TBL, and Dm must contain the fraction for surface interpolation. The ea fields in
the TBLSN instructions point to consecutive columns in a 3D table. The TBLS size
parameter must be word if the TBLSN size parameter is byte, and must be long word if
TBLSN is word. Increased size is necessary because a larger number of significant digits
is needed to accommodate the scaled fractional results of the 2D TBL.
5.3.5 Nested Subroutine Calls
The LINK instruction pushes an address onto the stack, saves the stack address at which
the address is stored, and reserves an area of the stack for use. Using this instruction in a
series of subroutine calls will generate a linked list of stack frames.
The UNLK instruction removes a stack frame from the end of the list by loading an
address into the SP and pulling the value at that address from the stack. When the
instruction operand is the address of the link address at the bottom of a stack frame, the
effect is to remove the stack frame from both the stack and the linked list.
5.3.6 Pipeline Synchronization with the NOP Instruction
Although the no operation (NOP) instruction performs no visible operation, it does force
synchronization of the instruction pipeline, since all previous instructions must complete
execution before the NOP begins.
5.4 PROCESSING STATES
This section describes the processing states of the CPU32. It includes a functional
description of the bits in the supervisor portion of the SR and an overview of actions taken
by the processor in response to exception conditions.
5-36
L0:
L1: . . .
MOVE.W
TBLSN.B
TBLSN.B
TBLS.W
ASR.L
BCC.B
ADDQ.B
Dx, Dl
Dx:Dl, Dm
#8, Dm
L1
#1, Dl
ea , Dx
ea Dl
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Copy entry number and fraction number
No round necessary
Surface interpolation, with round
Read just the result
Half round up
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