MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 38
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MC68340AG16E
Manufacturer Part Number
MC68340AG16E
Description
IC MPU 32BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68340FE25E.pdf
(441 pages)
Specifications of MC68340AG16E
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
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2.2 ADDRESS BUS
The address bus signals are outputs that define the address of the byte (or the most
significant byte) to be transferred during a bus cycle. The MC68340 places the address on
the bus at the beginning of a bus cycle. The address is valid while AS is asserted.
The address bus consists of the following two groups. Refer to Section 3 Bus Operation
for information on the address bus and its relationship to bus operation.
2.2.1 Address Bus (A23–A0)
These three-state outputs (along with A31–A24) provide the address for the current bus
cycle, except in the CPU address space.
2.2.2 Address Bus (A31–A24)
These pins can be programmed as the most significant eight address bits, port A parallel
I/O, or interrupt acknowledge signals. These pins can be used for more than one of their
multiplexed functions as long as the external demultiplexing circuit properly resolves
interaction between the different functions.
A31–A24
Port A7–A0
IACK7 – IACK1
This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or
from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two
bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the
2-4
2.3 DATA BUS (D15–D0)
These pins can function as the most significant eight address bits.
These eight pins can serve as a dedicated parallel I/O port. See Section 4 System
Integration Module for more information on programming these pins.
The MC68340 asserts one of these pins to indicate the level of an external interrupt
during an interrupt acknowledge cycle. Peripherals can use the IACK signals instead
of monitoring the address bus and function codes to determine that an interrupt
acknowledge cycle is in progress and to obtain the current interrupt level.
The terms assert and negate are used throughout this section
to avoid confusion when dealing with a mixture of active-low
and active-high signals. The term assert or assertion indicates
that a signal is active or true, independent of the level
represented by a high or low voltage. The term negate or
negation indicates that a signal is inactive or false.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
NOTE
MOTOROLA
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