MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 230

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

analyzed. To derive the actual instruction execution times for an instruction sequence, the
instruction times listed in the tables must be adjusted to account for overlap.
The formula for this calculation is as follows:
where:
The number of cycles for the instruction (C
addition to the raw number in the cycles column. In these cases, calculate overall
instruction time as if it were for multiple instructions, using the following equation:
where:
The overall head for the instruction is the head for the EA, and the overall tail for the
instruction is the tail for the operation. Therefore, the actual equation for execution time
becomes:
C
Every instruction must prefetch to replace itself in the instruction pipe. Usually, these
prefetches occur during or after an instruction. A prefetch is permitted to begin in the first
clock of any indexed EA mode operation.
Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of
an instruction provided the bus is not being used. If the bus is being used, then the
prefetch occurs at the next available time when the bus would otherwise be idle.
5.7.1.7 EFFECTS OF NEGATIVE TAILS. When the CPU32 changes instruction flow, the
instruction decode pipeline must begin refilling before instruction execution can resume.
Refilling forces a two-clock idle period at the end of the change-of-flow instruction. This
idle period can be used to prefetch an additional word on the new instruction path.
MOTOROLA
OP1
C
T
H
min (T
C
T
H
min (T
CEA is the instruction’s EA time
N
EA
N
N
OP
OP
is the tail time for instruction N
is the number of cycles listed for instruction N
is the head time for instruction N
is the EA’s tail time
is the instruction’s operation time
is the instruction operation’s head time
min (T
N
N
, H
, H
M
M
C
OP1
) is the minimum of parameters T
) is the minimum of parameters T
1
, H
min (T
EA2
Freescale Semiconductor, Inc.
)
1
For More Information On This Product,
, H
CEA
2
) C
CEA
MC68340 USER’S MANUAL
Go to: www.freescale.com
2
2
min (T
min (T
min (T
EA2
N
2
EA
) can include one or two EA calculations in
, H
, H
N
N
, H
3
and H
and H
) C
OP
OP2
)
) C
3
M
M
C
OP
min (T
OP2
3
min (T
, H
4
)
OP2
, H
EA3
)
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