ADE7569ASTZF16 Analog Devices Inc, ADE7569ASTZF16 Datasheet - Page 74

• Manufacturer Part Number: ADE7569ASTZF16
• Description: IC ENERGY METER MCU 16K 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7569ASTZF16

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Apparent Energy Pulse Output
All the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 circuitry has a pulse output whose frequency is
proportional to apparent power (see the Energy-to-Frequency
Conversion section). This pulse frequency output uses the
calibrated signal after VAGAIN. This output can also be used to
output a pulse whose frequency is proportional to I
output is active low and should preferably be connected to an
LED, as shown in Figure 80.
Line Apparent Energy Accumulation
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are designed with a special apparent energy
accumulation mode that simplifies the calibration process. By
using the on-chip, zero-crossing detection, the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
accumulate the apparent power signal in the LVAHR register
(Address 0x09) for an integral number of half cycles, as shown in
Figure 78. The line apparent energy accumulation mode is
always active.
The number of half-line cycles is specified in the LINCYC
register (Address 0x12), which is an unsigned 16-bit register.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can accumulate apparent power for up to 65,535
combined half cycles. Because the apparent power is integrated
on the same integral number of line cycles as the line active
register and reactive energy register, these values can easily be
compared. The energies are calculated more accurately because
of this precise timing control and provide all the information
needed for reactive power and power factor calculation.
At the end of an energy calibration cycle, the CYCEND flag (Bit 2)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set.
If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) is enabled, the 8052 core has a
pending ADE interrupt.
As for LWATTHR, when a new half-line cycle is written
in the LINCYC register (Address 0x12), the LVAHR register
(Address 0x09) is reset and a new accumulation starts at the next
zero crossing. The number of half-line cycles is then counted until
LINCYC is reached.
This implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register.
rms
. The pulse
Rev. B | Page 74 of 152
The line apparent energy accumulation uses the same signal
path as the apparent energy accumulation. The LSB size of these
two registers is equivalent.
Apparent Power No Load Detection
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 include a no load threshold feature on the apparent
power that eliminates any creep effects in the meter. The ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 accomplish
this by not accumulating energy if the multiplier output is below
the no load threshold. When the apparent power is below the
no load threshold, the VANOLOAD flag (Bit 2) in the Interrupt
Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the VANOLOAD
bit (Bit 2) is set in the Interrupt Enable 1 SFR (MIRQENL,
Address 0xD9), the 8052 core has a pending ADE interrupt.
The ADE interrupt stays active until the APNOLOAD status bit
is cleared (see the Energy Measurement Interrupts section).
The no load threshold level is selectable by setting the
VANOLOAD bits (Bits[5:4]) in the NLMODE register (Address
0x0E). Setting these bits to 0b00 disables the no load detection,
and setting them to 0b01, 0b10, or 0b11 sets the no load
detection threshold to 0.030%, 0.015%, and 0.0075% of the full-
scale output frequency of the multiplier, respectively.
This no load threshold can also be applied to the I
output when selected. In this case, the level of no load threshold
is the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In a tampering situation where no voltage is available to the energy
meter, the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 are capable of accumulating the ampere-hour instead of
apparent power into the VAHR, RVAHR, and LVAHR. When the
VARMSCFCON bit (Bit 3) of the MODE2 register (Address 0x0C)
is set, the VAHR, RVAHR, and LVAHR, and the input for the
digital-to-frequency converter accumulate I
power. All the signal processing and calibration registers
available for apparent power and energy accumulation remain
the same when ampere-hour accumulation is selected. However,
the scaling difference between I
independent values for gain calibration in the VAGAIN
(Address 0x1F), VADIV (Address 0x26), CFxNUM (Address
0x27 and Address 0x29), and CFxDEN (Address 0x28 and
Address 0x2A) registers.
rms
and apparent power requires
rms
instead of apparent
rms
pulse