ADE7569ASTZF16 Analog Devices Inc, ADE7569ASTZF16 Datasheet - Page 48

• Manufacturer Part Number: ADE7569ASTZF16
• Description: IC ENERGY METER MCU 16K 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7569ASTZF16

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Table 41. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD)
Bit
7
6
5
4
3
2
1
0
1
Table 42. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE)
Bit
7
6
5
4
3
2
1
0
Table 43. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9)
Bit
[7:6]
5
4
3
2
1
0
1
2
Table 44. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA)
Bit
7
6
5
4
3
2
1
0
1
This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
This function is not available in the ADE7566 or ADE7569.
This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
Interrupt Flag
RESET
Reserved
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Interrupt Flag
CF2
CF1
VAEOF
REOF
AEOF
VAEHF
REHF
AEHF
Interrupt Enable Bit
Reserved
FAULTSIGN
VARSIGN
APSIGN
VANOLOAD
RNOLOAD
APNOLOAD
Interrupt Enable Bit
CF2
CF1
VAEOF
REOF
AEOF
VAEHF
REHF
AEHF
1
1
1
1
2
2
1
Description
Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not
enabled by clearing Bit 2 of the MODE1 register.
Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not
enabled by clearing Bit 1 of the MODE1 register.
Logic 1 indicates that the VAHR register has overflowed.
Logic 1 indicates that the VARHR register has overflowed.
Logic 1 indicates that the WATTHR register has overflowed.
Logic 1 indicates that the VAHR register is half full.
Logic 1 indicates that the VARHR register is half full.
Logic 1 indicates that the WATTHR register is half full.
Description
Indicates the end of a reset (for both software and hardware reset).
Reserved.
Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).
Logic 1 indicates that the current channel has exceeded the IPKLVL value.
Logic 1 indicates that the voltage channel has exceeded the VPKLVL value.
Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.
Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles.
Logic 1 indicates detection of a zero crossing in the voltage channel.
Description
Reserved.
When this bit is set to Logic 1, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
Description
When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
Rev. B | Page 48 of 152