ADE7569ASTZF16 Analog Devices Inc, ADE7569ASTZF16 Datasheet - Page 34

• Manufacturer Part Number: ADE7569ASTZF16
• Description: IC ENERGY METER MCU 16K 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7569ASTZF16

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can be configured to generate a PSM interrupt when
the source of V
battery switchover. Setting the EBSO bit in the power manage-
ment interrupt enable SFR (IPSME, Address 0xEC) enables this
event to generate a PSM interrupt (see Table 21).
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 can also be configured to generate an interrupt when
the source of V
the V
the power management interrupt enable SFR (IPSME, Address
0xEC) enables this event to generate a PSM interrupt.
The flags in the IPSMF SFR for these interrupts, FBSO and
FPSR, are set regardless of whether the respective enable bits
have been set. The battery switchover and power supply restore
event flags, FBSO and FPSR, are latched. These events must be
cleared by writing a 0 to these bits. Bit 6 (VSWSOURCE) in the
peripheral configuration SFR (PERIPH, Address 0xF4) tracks
the source of V
V
V
The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 can be
configured to generate a PSM interrupt when V
magnitude by more than a configurable threshold. This threshold
is set in the temperature and supply delta SFR (DIFFPROG,
Address 0xF3), which is described in Table 50. See the External
Voltage Measurement section for more information. Setting the
EVADC bit in the power management interrupt enable SFR
(IPSME, Address 0xEC) enables this event to generate a PSM
interrupt. Note that this feature is not available in the ADE7116.
The V
measurements take place in the background at intervals to check
the change in V
the start ADC measurement SFR (ADCGO, Address 0xD8), as
described in Table 51. The FVADC flag in the power manage-
ment interrupt flag SFR (IPSMF, Address 0xF8) indicates when
a V
Measurement section for details on how V
DD
DCIN
DCIN
and cleared when V
DD
ADC PSM Interrupt
DCIN
measurement is ready. See the External Voltage
power supply has been restored. Setting the EPSR bit in
voltage is measured using a dedicated ADC. These
DCIN
SWOUT
SWOUT
SWOUT
. Conversions can also be initiated by writing to
. The bit is set when V
changes from V
changes from V
SWOUT
is connected to V
DD
BAT
to V
to V
SWOUT
DCIN
BAT
DD
, indicating
, indicating that
is measured.
BAT
DCIN
is connected to
.
changes
Rev. B | Page 34 of 152
V
The V
measurements take place in the background at intervals to
check the change in V
level is lower than the threshold set in the battery detection
threshold SFR (BATVTH, Address 0xFA), described in Table 52,
or when a new measurement is ready in the battery ADC value
SFR (BATADC, Address 0xDF), described in Table 54. See the
Battery Measurement section for more information. Setting the
EBAT bit in the power management interrupt enable SFR
(IPSME, Address 0xEC) enables this event to generate a PSM
interrupt. Note that this feature is not available in the ADE7116.
V
The V
bit in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set when the V
1.2 V. Setting the EVDCIN bit in the IPSME SFR enables this
event to generate a PSM interrupt. This event, which is associated
with the SAG monitoring, can be used to detect that a power
supply (V
prior to initiating a switch from V
feature is not available in the ADE7116.
SAG Monitor PSM Interrupt
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 energy measurement DSP monitors the ac voltage
input at the V
(Address 0x14) is used to set the threshold for a line voltage
SAG event. The FSAG bit in the power management interrupt
flag SFR (IPSMF, Address 0xF8) is set if the line voltage stays
below the level set in the SAGLVL register for the number of
line cycles set in the SAGCYC register (Address 0x13). See the
Line Voltage SAG Detection section for more information.
Setting the ESAG bit in the power management interrupt enable
SFR (IPSME, Address 0xEC) enables this event to generate a
PSM interrupt.
BAT
DCIN
Monitor PSM Interrupt
Monitor PSM Interrupt
BAT
DCIN
voltage is measured using a dedicated ADC. These
DD
voltage is monitored by a comparator. The FVDCIN
) is compromised and to trigger further actions
P
and V
N
BAT
input pins. The SAGLVL register
. The FBAT bit is set when the battery
DCIN
DD
input level is lower than
to V
BAT
. Note that this