ADE7569ASTZF16 Analog Devices Inc, ADE7569ASTZF16 Datasheet - Page 103

• Manufacturer Part Number: ADE7569ASTZF16
• Description: IC ENERGY METER MCU 16K 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7569ASTZF16

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 95. LCD Segment Enable SFR (LCDSEGE, Address 0x97)
Bit
7
6
5
4
3
2
[1:0]
Table 96. LCD Pointer SFR (LCDPTR, Address 0xAC)
Bit
7
6
[5:0]
Table 97. LCD Data SFR (LCDDAT, Address 0xAE)
Bit
[7:0]
Table 98. LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED)
Bit
[7:4]
3
2
1
0
LCD SETUP
The LCD configuration SFR (LCDCON, Address 0x95)
configures the LCD module to drive the type of LCD in the user
end system. The BIAS bit (Bit 2) and the LMUX bits in this SFR
should be set according to the LCD specifications.
The COM2/FP28 and COM3/FP27 pins default to LCD segment
lines. Selecting the 3× multiplex level in the LCD configuration
SFR (LCDCON, Address 0x95) by setting LMUX[1:0] to 10
changes the FP28 pin functionality to COM2. The 4× multiplex
level selection, LMUX[1:0] = 11, changes the FP28 pin
functionality to COM2 and the FP27 pin functionality to
COM3.
The LCD segments of FP0 to FP15 and FP26 are enabled by
default. Additional pins are selected for LCD functionality in
the LCD segment enable SFR (LCDSEGE, Address 0x97) and
LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED) where
there are individual enable bits for the FP16 to FP25 segment
pins. The LCD pins do not have to be enabled sequentially. For
example, if the alternate function of FP23, the Timer 2 input, is
required, any of the other shared pins, FP16 to FP25, can be
enabled instead.
Mnemonic
FP25EN
FP24EN
FP23EN
FP22EN
FP21EN
FP20EN
Reserved
Mnemonic
Reserved
FP19EN
FP18EN
FP17EN
FP16EN
Mnemonic
R/W
Reserved
ADDRESS
Mnemonic
LCDDATA
Default
0
0
0
0
0
0
0
Default
0
0
0
0
0
Default
0
Default
0
0
0
Description
FP25 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP24 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP23 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP22 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP21 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP20 function select bit. 0 = general-purpose I/O, 1 = LCD function.
These bits must be kept at 0 for proper operation.
Description
Read or write LCD bit. If this bit is set to 1, the data in LCD data SFR (LCDDAT, Address 0xAE) is
written to the address indicated by the ADDRESS bits (LCDPTR, Address 0xAC).
Reserved.
LCD memory address (see Table 99).
Description
Reserved.
FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function.
FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.
Description
Data to be written into or read out of the LCD memory SFRs.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 103 of 152
The Display Element Control section contains details about
setting up the LCD data memory to turn individual LCD
segments on and off. Setting the LCDRST bit (Bit 6) in the LCD
Configuration SFR (LCDCON, Address 0x95) resets the LCD
data memory to its default (0). A power-on reset also clears the
LCD data memory.
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and
discharged at a certain rate. This rate, the refresh rate, determines
the visual characteristics of the LCD. A slow refresh rate results
in the LCD blinking on and off between refreshes. A fast refresh
rate presents a screen that appears to be continuously lit. In
addition, a faster refresh rate consumes more power.
The frame rate, or refresh rate, for the LCD module is derived
from the LCD clock, f
or 128 Hz by the CLKSEL bit (Bit 3) in the LCD Configuration
SFR (LCDCON, Address 0x95). The minimum refresh rate
needed for the LCD to appear solid (without blinking) is
independent of the multiplex level.
LCDCLK
. The LCD clock is selected as 2048 Hz