CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 59

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

HSS Receive Address Register [0xC078] [R/W]
Table 94. HSS Receive Address Register
Register Description
The HSS Receive Address register is used as the base pointer
address for the next HSS block receive transfer.
HSS Receive Counter Register [0xC07A] [R/W]
Table 95. HSS Receive Counter Register
Register Description
The HSS Receive Counter register designates the block byte
length for the next HSS receive transfer. Load this register with
the word count minus one to start the block receive transfer. As
each byte is received this register value is decremented. When
read, this register indicates the remaining length of the transfer.
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
R/W
15
15
0
7
0
0
7
0
-
R/W
R/W
R/W
14
14
0
6
0
0
6
0
-
R/W
R/W
R/W
13
13
0
5
0
0
5
0
-
Reserved
R/W
R/W
R/W
12
12
0
4
0
0
4
0
-
Address...
...Address
...Counter
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS
block receive transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one
giving a maximum value of 0x03FF (1023) or 2048 bytes. When
the transfer is complete this register returns 0x03FF until
reloaded.
Reserved
Write all reserved bits with ’0’.
R/W
R/W
R/W
11
11
0
3
0
0
3
0
-
R/W
R/W
R/W
10
10
0
2
0
0
2
0
-
R/W
R/W
R/W
R/W
9
0
1
0
9
0
1
0
Counter...
CY7C67300
Page 59 of 99
R/W
R/W
R/W
R/W
8
0
0
0
8
0
0
0
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