CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 44

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

supported in Port 1A). This bit is only available for Device 1 and
is a reserved bit in Device 2.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID
interrupt. When enabled, this interrupt triggers on both the rising
and falling edge of the OTG ID pin (only supported in Port 1A).
This bit is only available for Device 1 and is a reserved bit in
Device 2.
1: Enable ID interrupt
0: Disable ID interrupt
SOF/EOP Timeout Interrupt Enable (Bit 11)
The SOF/EOP Timeout Interrupt Enable bit enables or disables
the SOF/EOP Timeout Interrupt. When enabled this interrupt
triggers when the USB host fails to send a SOF or EOP packet
within the time period specified in the Device n SOF/EOP Count
register. In addition, the Device n Frame register counts the
number of times the SOF/EOP Timeout Interrupt triggers
between receiving SOF/EOPs.
1: SOF/EOP timeout occurred
0: SOF/EOP timeout did not occur
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the
SOF/EOP received interrupt.
1: Enable SOF/EOP received interrupt
0: Disable SOF/EOP received interrupt
Reset Interrupt Enable (Bit 8)
The Reset Interrupt Enable bit enables or disables the USB
Reset Detected interrupt
1: Enable USB Reset Detected interrupt
0: Disable USB Reset Detected interrupt
EP7 Interrupt Enable (Bit 7)
The EP7 Interrupt Enable bit enables or disables endpoint seven
(EP7) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses trigger this interrupt.
1: Enable EP7 Transaction Done interrupt
0: Disable EP7 Transaction Done interrupt
EP6 Interrupt Enable (Bit 6)
The EP6 Interrupt Enable bit enables or disables endpoint six
(EP6) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Document #: 38-08015 Rev. *J
Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses trigger this interrupt.
1: Enable EP6 Transaction Done interrupt
0: Disable EP6 Transaction Done interrupt
EP5 Interrupt Enable (Bit 5)
The EP5 Interrupt Enable bit enables or disables endpoint five
(EP5) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses trigger this interrupt.
1: Enable EP5 Transaction Done interrupt
0: Disable EP5 Transaction Done interrupt
EP4 Interrupt Enable (Bit 4)
The EP4 Interrupt Enable bit enables or disables endpoint four
(EP4) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses trigger this interrupt.
1: Enable EP4 Transaction Done interrupt
0: Disable EP4 Transaction Done interrupt
EP3 Interrupt Enable (Bit 3)
The EP3 Interrupt Enable bit enables or disables endpoint three
(EP3) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses trigger this interrupt.
1: Enable EP3 Transaction Done interrupt
0: Disable EP3 Transaction Done interrupt
EP2 Interrupt Enable (Bit 2)
The EP2 Interrupt Enable bit enables or disables endpoint two
(EP2) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses trigger this interrupt.
1: Enable EP2 Transaction Done interrupt
0: Disable EP2 Transaction Done interrupt
EP1 Interrupt Enable (Bit 1)
The EP1 Interrupt Enable bit enables or disables endpoint one
(EP1) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events
occur in a transaction for the device’s supplied Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception
CY7C67300
Page 44 of 99
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